W256

Rev 1.0, November 25, 2006

Page 2 of 7

Pin Summary

Name

Pins

Description

SEL_DDR

28

Input to configure for DDR-ONLY mode or STANDARD SDRAM mode.

1 = DDR-ONLY mode.

0 = STANDARD SDRAM mode.

When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, all the buffers

will be configured as DDR outputs.

Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.

When SEL_DDR is pulled LOW or configured for STANDARD SDRAM output, all

the buffers will be configured as STANDARD SDRAM outputs.

Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM mode.

SCLK

16

SMBus clock input.

SDATA

15

SMBus data input.

BUF_IN

10

Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V input for

STANDARD SDRAM mode.

FBOUT

1

Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.

PWR_DWN#

2

Active LOW input to enable Power Down mode; all outputs will be pulled LOW.

DDR[0:5]T_SDRAM

[0,2,4,6,8,10]

3, 7, 12, 19, 23, 27

Clock outputs. These outputs provide copies of BUF_IN. Voltage swing depends

on VDD3.3_2.5 power supply.

DDR[0:5]C_SDRAM

[1,3,5,7,9, 11]

4, 8, 13, 18, 22, 26

Clock outputs. These outputs provide complementary copies of BUF_IN when

SEL_DDR is active. These outputs provide copies of BUF_IN when SEL_DDR is

inactive. Voltage swing depends on VDD3.3_2.5 power supply.

VDD3.3_2.5

5, 9, 14, 21, 25

Connect to 2.5V power supply when W256 is configured for DDR-ONLY mode.

Connect to 3.3V power supply, when W256 is configured for standard SDRAM

mode.

GND

6, 11, 17, 20, 24

Ground.