LTC1063

9

1063fa

CLOCK FREQUENCY (MHz)

0.5

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

2.5

1063 F06

1.0

1.5

2.0

3.0

fCLK = K/RC

C = 10pF

TA = 25°C

VS = ±7.5V

VS = ±2.5V

VS = ±5V

CLOCK FREQUENCY (kHz)

0

4

3

2

1

0

–1

–2

–3

–4

400

1063 F05

100

200

300

500

C = 200pF

TA = –40°C

TA = 85°C

VS = ±2.5V

VS = ±5V

VS = ±7.5V

VS = ±7.5V

VS = ±5V

VS = ±2.5V

INTERNAL CLOCK FREQUENCY (kHz)

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

1063 F04b

100

300

500

VS = ±7.5V

VS = ±2.5V

FCLK = K/RC

C = 200pF

TA = 25°C

VS = ±5V

200

400

VIN

R

VOUT

1063 F04a

C

V–

V+

1

2

3

4

8

7

6

5

LTC1063

Self-Clocking Operation

The LTC1063 features an internal oscillator which can be

tuned via an external RC. The LTC1063’s internal oscillator

is primarily intended for generation of clock frequencies

below 500kHz. The first curve of the Typical Performance

Characteristics section shows how to quickly choose the

value of the RC for a given frequency. More precisely, the

frequency of the internal oscillator is equal to:

fCLK = K/RC

For clock frequencies (fCLK) below 100kHz, K equals 1.07.

Figure 4b shows the variation of the parameter K versus

clock frequency and power supply. First choose the de-

sired clock frequency, (fCLK < 500kHz), then through

Figure 4b pick the right value of K, set C = 200pF and solve

for R.

Example 1: fCUTOFF = 2kHz, fCLK = 200kHz, VS = ±5V,

TA = 25°C, K = 1.0, C = 200pF

then,

R = (1.0)/(200kHz

× 204pF) = 24.5k.

Figure 4b. fCLK vs K

Note a 4pF parasitic capacitance is assumed in parallel

with the external 200pF timing capacitor. Figure 5 shows

the clock frequency variation from – 40

°C to 85°C. The

200kHz clock of Example 1 will change by –1.75% at 85

°C.

Figure 5. fCLK vs Temperature

For a very limited temperature range, the internal oscillator

of the LTC1063 can be used to generate clock frequencies

above 500kHz (Figures 6 and 7). The data of Figure 6 is

derived from several devices. For a given external (RC)

value, the observed device-to-device clock frequency varia-

tion was

±1% (VS = ±5V), and ±1.25% for VS = ±2.5V.

Example 2:

fCUTOFF = 20kHz, fCLK = 2MHz, VS = ±7.5V,

TA = 25°C, C = 10pF

from Figure 6, K = 0.575,

and,

R = (0.575)/(2MHz

× 14pF) = 20.5k.

Figure 6. fCLK vs K

Figure 4a.

APPLICATIO S I FOR ATIO