AD8368

Rev. A | Page 12 of 20

CIRCUIT DESCRIPTION

The AD8368 is a single-ended VGA with a bandwidth of 800 MHz

and a gain control span of 34 dB ranging from −12 dB to +22 dB.

It incorporates an uncommitted square law detector that can be

used to form a tight AGC loop around the VGA. Using the

Analog Devices patented X-AMP architecture, the AD8368

achieves accurate linear-in-dB gain control with excellent linearity

(OIP3) and noise figure (NF). The part also features 50 Ω input

and output impedances for ease of use.

The main signal path, shown in Figure 30, consists of a variable

input attenuator followed by a fixed-gain amplifier and output

buffer. This architecture allows for a constant OIP3 and output

noise floor as a function of gain setting. As a result, NF and IIP3

increase 1 dB for every 1 dB decrease in gain, resulting in a part

with constant dynamic range over gain setting.

ATTENUATOR LADDER

DECL

50Ω

0dB –2dB –4dB

–36dB

VOUT

INPT

GAIN

MODE

GAIN INTERPOLATOR

FIXED-GAIN

AMPLIFIER

OUTPUT

BUFFER

Figure 30. Simplified Block Diagram

INPUT ATTENUATOR AND INTERPOLATOR

The input attenuator is built from an 18-section resistor ladder

providing 2 dB of attenuation at each successive tap point. The

resistor ladder acts as a linear input attenuator, in addition to

providing an accurate 50 Ω input impedance. The variable

signal from the appropriate tap point along the ladder and feed

this signal to the fixed-gain amplifier. To realize a continuous

gain control function from discrete tap points, the gain

interpolator creates a weighted sum of signals appearing on

FIXED-GAIN STAGE AND OUTPUT BUFFER

The weighted sum of the different tap points is fed into the

fixed-gain stage that drives the output buffer. Because the

resistive input attenuator is linear and contributes minimal

noise as a passive termination, the dynamic range as a function

of gain is determined primarily by the noise and the distortion

of the fixed-gain amplifier. This architecture explains the

constant OIP3 and constant output noise floor with gain setting

and the corresponding dB-for-dB increase in IIP3 and NF with

decreasing gain. The output buffer has 6 dB of gain and

provides a broadband 50 Ω single-ended output impedance.

OUTPUT OFFSET CORRECTION

The dc level at the input, INPT, is driven by an internal

OUTP, is regulated to the same midsupply reference by an offset

correction loop independent of gain setting, temperature, and

process. The low-pass response of this loop creates a high-pass

corner frequency in the signal path transfer function, which can

VOUT

FIXED-GAIN

AMPLIFIER

FROM

INTERPOLATOR

OUTPUT

BUFFER

×1

DECL

HPFL

Figure 31. Output Centering Control Loop

The input and output coupling capacitors should be selected to

provide low impedances at the frequencies of interest relative to

50 Ω so as not to affect the high-pass corner. In this case, the

which form independent poles in the feedback path of the offset

correction loop. The high-pass corner is determined by the

highest of these poles, which are given by:

)

005

.

0

(

8

.

0

)

kHz

(

,

HPFL

HPFL

HP

C

f

+

=

)

005

.

0

(

5700

)

kHz

(

,

DECL

DECL

HP

C

f

+

=

When using this method to set the high-pass frequency, the

other capacitor should be sized such that its pole is at least 30×

total decoupling capacitance at the DECL pins.

INPUT AND OUTPUT IMPEDANCES

The AD8368 offers single-ended broadband 50 Ω input and

output impedances. The excellent match to 50 Ω is maintained

from part to part, over frequency, and over gain setting. Both

the input and output pins must be externally ac-coupled to

prevent disruption of the internal dc levels. Sufficiently large

coupling capacitors should be used so that their impedance is

negligible relative to the 50 Ω presented by the ladder at the

input and by the output buffer at the output.