1024-Bit EEPROM iButton

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19

Improved Network Behavior

(Switchpoint Hysteresis)

In a 1-Wire environment, line termination is possible

only during transients controlled by the bus master

(1-Wire driver). 1-Wire networks, therefore, are suscep-

tible to noise of various origins. Depending on the

physical size and topology of the network, reflections

from end points and branch points can add up or can-

cel each other to some extent. Such reflections are visi-

ble as glitches or ringing on the 1-Wire communication

line. Noise coupled onto the 1-Wire line from external

sources can also result in signal glitching. A glitch dur-

ing the rising edge of a time slot can cause a slave

device to lose synchronization with the master and,

consequently, result in a Search ROM command com-

ing to a dead end or cause a device-specific function

command to abort. For better performance in network

applications, the DS1972 uses a new 1-Wire front-end,

which makes it less sensitive to noise.

The DS1972’s 1-Wire front-end differs from traditional

slave devices in three characteristics.

1) There is additional lowpass filtering in the circuit that

detects the falling edge at the beginning of a time

slot. This reduces the sensitivity to high-frequency

noise. This additional filtering does not apply at

overdrive speed.

2) There is a hysteresis at the low-to-high switching

threshold VTH. If a negative glitch crosses VTH but

does not go below VTH - VHY, it is not recognized

(Figure 12, Case A). The hysteresis is effective at

any 1-Wire speed.

3) There is a time window specified by the rising edge

hold-off time tREH during which glitches are ignored,

even if they extend below the VTH - VHY threshold

(Figure 12, Case B, tGL < tREH). Deep voltage drops

or glitches that appear late after crossing the VTH

threshold and extend beyond the tREH window can-

not be filtered out and are taken as the beginning of a

new time slot (Figure 12, Case C, tGL

≥ tREH).

Devices that have the parameters VHY and tREH speci-

fied in their electrical characteristics use the improved

1-Wire front-end.

CRC Generation

The DS1972 uses two different types of CRCs. One

CRC is an 8-bit type and is stored in the most signifi-

cant byte of the 64-bit ROM. The bus master can com-

pute a CRC value from the first 56 bits of the 64-bit

ROM and compare it to the value stored within the

DS1972 to determine if the ROM data has been

received error-free. The equivalent polynomial function

of this CRC is X8 + X5 + X4 + 1. This 8-bit CRC is

received in the true (noninverted) form. It is computed

at the factory and lasered into the ROM.

The other CRC is a 16-bit type, generated according to

the standardized CRC-16 polynomial function X16 + X15

+ X2 + 1. This CRC is used for fast verification of a data

transfer when writing to or reading from the scratchpad.

In contrast to the 8-bit CRC, the 16-bit CRC is always

communicated in the inverted form. A CRC generator

inside the DS1972 iButton (Figure 13) calculates a new

16-bit CRC, as shown in the command flowchart

(Figure 7). The bus master compares the CRC value

read from the device to the one it calculates from the

data and decides whether to continue with an operation

or to reread the portion of the data with the CRC error.

With the Write Scratchpad command, the CRC is gen-

erated by first clearing the CRC generator and then

shifting in the command code, the target addresses

TA1 and TA2, and all the data bytes as they were sent

VPUP

VTH

VHY

0V

tREH

tGL

tREH

tGL

CASE A

CASE C

CASE B

Figure 12. Noise Suppression Scheme