CY28323PVC

Rev 1.0, November 24, 2006

Page 15 of 21

Program the CPU Output Frequency

When the programmable output frequency feature is enabled

(Pro_Freq_EN bit is set), the CPU output frequency is deter-

mined by the following equation:

Fcpu = G * (N+3)/(M+3)

“N” and “M” are the values programmed in Programmable

Frequency Select N-Value Register and M-Value Register,

respectively.

“G” stands for the PLL Gear Constant, which is determined by

the programmed value of FS[4:0] or SEL[4:0]. The value is

listed in

Table 4.

The ratio of (N+3) and (M+3) need to be greater than “1”

[(N+3)/(M+3) > 1].

The following table lists set of N and M values for different

frequency output ranges.This example use a fixed value for

the M-Value Register and select the CPU output frequency by

changing the value of the N-Value Register.

WD_TIMER[4:0]

These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the

prescaler.

The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler

is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.

When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.

WD_PRE_SCALER

0 = 150 ms

1 = 2.5 sec

RST_EN_WD

This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs.

0 = Disabled

1 = Enabled

RST_EN_FC

This bit will enable the generation of a Reset pulse after a frequency change occurs.

0 = Disabled

1 = Enabled

Table 5. Register Summary (continued)

Name

Description

Table 6. Examples of N and M Value for Different CPU Frequency Range

Frequency Ranges

Gear Constants

Fixed Value for

M-Value Register

Range of N-Value Register

for Different CPU Frequency

50 MHz–129 MHz

48.00741

93

97–255

130 MHz–248 MHz

48.00741

45

127–245