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Figure 15.

2.5

ADR4: WDC Watchdog Control Register

Figure 16.

The Startup Watchdog is not programmable and will always generate a 1.0ms low cycle on NRESET followed

by a 320ms high cycle until an Acknowledgment will occur. If no Acknowldege is received after the 7th cycle,

the device will automatically be forced into Sleep mode.

Acknowledgment and Reset of Startup and Window Watchdog is automatically performed by overwriting

(or rewriting) this register.

Note, that with WDEN set, a cyclic setting of IFR.WKW after the programmed Wakeup time will occur.

2.5.1 Watchdog configuration:

“No Request”

“2.5ms cycle

on NINT”

“Finish Cycle”

“Update ADJ”

CG=01

CG=10

CG=00

CG=11

State transition during oscillator calibration

Watchdog and Interrupt

Start time measurement

at rising edge

Calculate

Offset

Write offset

Watchdog and Interrupt can be enabled

has to be disabled

SWT0

WDT3

SWT1

WND

WDEN

WDT2

WDT1

WDT0

D7

D0

Wakeup Watchdog

timing configuration

0000 : 80ms

0001 : 160ms

0010 : 320ms

0011 : 640ms

0100 : 800ms

1000 : 1sec

1001 : 2sec

1010 : 4sec

1011 : 8sec

1100 : 45min

Software Window Watchdog

timing configuration

00 : 2.5 - 5ms

01 : 5 - 10ms

10 : 10 - 20ms

11 : 20 - 40ms

Enable Wakeup Watchdog,

Window Watchdog will be

automatically deactivated

until wakeup watchdog expires

Reserved bits (‘RES’) have to be written as ‘0’.

Disable

Window Watchdog,

only allowed with

PGEN set, see

previous table

for Osc adjust