GENERAL DESCRIPTION

The ISB35000 array series uses a high perform-

ance, low voltage, triple level metal, HCMOS 0.5

micron process to achieve sub-nanosecond inter-

nal speeds while offering very low power dissipation

and high noise immunity. The potential total gate

count ranges above 1 million equivalent usable

gates. The array operates over a Vdd voltage range

of 2.7 to 3.6 volts.

The I/O count for this array family ranges to over

600 signals and 1000 pins dependent upon the

package technology utilized. A Sea of I/O approach

has been followed to give a solution to today’s

problems of drive levels and specialized interface

standards. The array does not utilize a set bond pad

spacing but allows for pad spacings from 80 mi-

crons upwards.

The I/O can be configured for circuits ranging from

low voltage CMOS and TTL to 200 mHz plus low

swing differential circuits. Standards like GTL,

SCSI-2, 3.3 Volt PCI, CTI, and a limited set of 5.0

Volt interfaces are currently being addressed. A

specialized set of impedance matched transmis-

sion line driver LVTTL type circuits are also avail-

able with 25, 35, 45, and 55 Ohm output

impedance. These buffers sacrifice direct current

capabilities for matching positive and negative volt-

age and current waveforms.

CONVENTIONAL VIA LAYOUT

STACKED VIA LAYOUT

- STACKABLE CONTACTS + VIAs ALLOW MUCH HIGHER DENSITY (AREA SAVINGS UP TO 20% FOR R.L.)

- SIMPLIFIED ROUTING AND DESIGN RULE CHECKING

SUBSTRATE

ISOLATION

GATE

1st DIELECTRIC

2nd DIELECTRIC

CONTACT

CONTACT/VIA

PLUGS

1st

VIA

METAL 1

METAL 2

METAL 3

2nd

VIA

3rd DIELECTRIC

ISB35_VA

Figure 1. Advantages of stacked contacts and vias

ISB35000 SERIES

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