6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

VIK

Input clamp voltage II = –18 mA, VEN = 0

–1.2

V

IIH

I/O input high

leakage

VI = 5 V, VEN = 0

5.0

µA

ICCBA

Vref_B to Vref_A

leakage

Vref_B = VEN = 5.5 V, Vref_A = 4.5 V, IO = 0, VI = VCC or GND

1

µA

CI(ref_A/B/EN)

Input capacitance

VI = 3 V or 0

11

pF

Cio(off)

I/O pin off-state

capacitance

VO = 3 V or 0, VEN = 0

4.0

6.0

pF

Cio(on)

I/O Pin on-state

capacitance

VO = 3 V or 0, VEN = 3 V

10.5

12.5

pF

ron (2)

On-state resistance

VI = 0, IO = 64 mA

Vref_A = 3.3 V; Vref_B = VEN = 5 V

8.0

Ω

Vref_A = 1.8 V; Vref_B = VEN = 5 V

9.0

Vref_A = 1.0 V; Vref_B = VEN = 5 V

10

VI = 0, IO = 32 mA

Vref_A = 1.8 V; Vref_B = VEN = 5 V

10

Ω

Vref_A = 2.5 V; Vref_B = VEN = 5 V

15

VI = 1.8 V, IO = 15 mA

Vref_A = 3.3 V; Vref_B = VEN = 5 V

9.0

Ω

VI = 1.0 V, IO = 10 mA

Vref_A = 1.8 V; Vref_B = VEN = 3.3 V

18

Ω

VI = 0 V, IO = 10 mA

Vref_A = 1.0 V; Vref_B = VEN = 3.3 V

20

Ω

VI = 0 V, IO = 10 mA

Vref_A = 1.0 V; Vref_B = VEN = 1.8 V

30

Ω

(1)

All typical values are at TA = 25°C.

(2)

Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined

by the lowest voltage of the two (A or B) pins.

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LSF0102-Q1

SDLS969B – MAY 2018 – REVISED MAY 2023

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