CC113LRGPR.B datasheet(30/87 Pages) TI2

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CC113L

SWRS108B – MAY 2011 – REVISED JUNE 2014

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When using the auto flush function, the maximum packet length is 63 bytes in variable packet length mode

and 64 bytes in fixed packet length mode. Note that when PKTLEN.APPEND_STATUS is enabled, the

maximum allowed packet length is reduced by two bytes in order to make room in the RX FIFO for the two

status bytes appended at the end of the packet. Since the entire RX FIFO is flushed when the CRC check

fails, the previously received packet must be read out of the FIFO before receiving the current packet. The

MCU must not read from the current packet until the CRC has been checked as OK.

5.10.3 Packet Handling in Receive Mode

In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word.

When found, the demodulator has obtained both bit and byte synchronization and will receive the first

payload byte.

When variable packet length mode is enabled, the first byte is the length byte. The packet handler stores

this value as the packet length and receives the number of bytes indicated by the length byte. If fixed

packet length mode is used, the packet handler will accept the programmed number of bytes.

Next, the packet handler optionally checks the address and only continues the reception if the address

matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the

appended CRC checksum.

At the end of the payload, the packet handler will optionally write two extra packet status bytes (see

Table 5-5 and Table 5-6) that contain CRC status, link quality indication, and RSSI value.

5.10.4 Packet Handling in Firmware

When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet

has been received. Additionally, for packets longer than 64 bytes, the RX FIFO needs to be read while in

RX. There are two possible solutions to get the necessary status information:

a. Interrupt Driven Solution

The GDO pins can be used to give an interrupt when a sync word has been received or when a complete

packet has been received by setting IOCFGx.GDOx_CFG=0x06. In addition, there are two configurations

for the IOCFGx.GDOx_CFG register that can be used as an interrupt source to provide information on

how many bytes that are in the RX FIFO (IOCFGx.GDOx_CFG=0x00 and IOCFGx.GDOx_CFG=0x01).

See Table 5-15 for more information.

b. SPI Polling

The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and

GDO0 values respectively. The RXBYTES register can be polled at a given rate to get information about

the number of bytes in the RX FIFO. Alternatively, the number of bytes in the RX FIFO can be read from

the chip status byte returned on the MISO line each time a header byte, data byte, or command strobe is

sent on the SPI bus.

It is recommended to employ an interrupt driven solution since high rate SPI polling reduces the RX

sensitivity. Furthermore, as explained in Section 5.5.3 and the CC113L Errata Notes SWRZ038, when

using SPI polling, there is a small, but finite, probability that a single read from registers PKTSTATUS, and

RXBYTES is being corrupt. The same is the case when reading the chip status byte.

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