CC113LRGP datasheet(65/87 Pages) TI2

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CC113L

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SWRS108B – MAY 2011 – REVISED JUNE 2014

Table 5-55. 0x26: FSCAL0 - Frequency Synthesizer Calibration

Bit

Field Name

Reset

R/W

Description

Not used

Frequency synthesizer calibration control. The value to use in this

6:0

FSCAL0[6:0]

13 (0x0D)

R/W

5.21.2 Configuration Register Details - Registers that Loose Programming in SLEEP State

Table 5-56. 0x29: RESERVED

Bit

Field Name

Reset

R/W

Description

7:0

89 (0x59)

R/W

Use setting from SmartRF Studio SWRC176

Table 5-57. 0x2A: RESERVED

Bit

Field Name

Reset

R/W

Description

7:0

127 (0x7F)

R/W

Use setting from SmartRF Studio SWRC176

Table 5-58. 0x2B: RESERVED

Bit

Field Name

Reset

R/W

Description

7:0

63 (0x3F)

R/W

Use setting from SmartRF Studio SWRC176

Table 5-59. 0x2C: TEST2 - Various Test Settings

Bit

Field Name

Reset

R/W

Description

Use setting from SmartRF Studio SWRC176

This register will be forced to 0x88 or 0x81 when it wakes up from

SLEEP mode, depending on the configuration of

FIFOTHR.ADC_RETENTION.

7:0

TEST2[7:0]

136 (0x88)

R/W

The value read from this register when waking up from SLEEP

always is the reset value (0x88) regardless of the

ADC_RETENTION setting. The inverting of some of the bits due to

the ADC_RETENTION setting is only seen INTERNALLY in the

analog part.

Table 5-60. 0x2D: TEST1 - Various Test Settings

Bit

Field Name

Reset

R/W

Description

Use setting from SmartRF Studio SWRC176

This register will be forced to 0x31 or 0x35 when it wakes up from

SLEEP mode, depending on the configuration of

FIFOTHR.ADC_RETENTION.

7:0

TEST1[7:0]

49 (0x31)

R/W

The value read from this register when waking up from SLEEP

always is the reset value (0x31) regardless of the

ADC_RETENTION setting. The inverting of some of the bits due to

the ADC_RETENTION setting is only seen INTERNALLY in the

analog part.

Table 5-61. 0x2E: TEST0 - Various Test Settings

Bit

Field Name

Reset

R/W

Description

7:2

TEST0[7:2]

2 (000010)

R/W

Use setting from SmartRF Studio SWRC176

VCO_SEL_CAL_EN

R/W

Enable VCO selection calibration stage when 1

TEST0[0]

R/W

Use setting from SmartRF Studio SWRC176

Detailed Description

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