5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN

MAX

UNIT

Supply voltage range, VCC

–0.3

2.3

V

Voltage range at any input or output terminal

Differential I/O

–0.3

1.5

V

CMOS Inputs

–0.3

2.3

V

Junction temperature, TJ

-40

105

°C

Storage temperature, Tstg

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

5.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2)

±500

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VCC

Main power supply

1.62

1.8

1.98

V

TA

Operating free-air temperature

–40

85

°C

C(AC)

AC coupling capacitor required for TX pins

75

200

nF

V(PSN)

AC coupling capacitor required for TX pins

100

mV

t(VCC_RAMP)

VCC supply ramp requirement

0.2

40

ms

R(pullup-down)

Pull-up/down resistor to control CNF pins

2.2

kΩ

5.4 Thermal Information

THERMAL METRIC(1)

TUSB542

UNIT

X2QFN (RWQ)

18 PINS

RθJA

Junction-to-ambient thermal resistance

83.4

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

52

°C/W

RθJB

Junction-to-board thermal resistance

49.1

°C/W

ψJT

Junction-to-top characterization parameter

0.6

°C/W

ψJB

Junction-to-board characterization parameter

49.1

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

n/a

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TUSB542

SLLSER3F – DECEMBER 2015 – REVISED DECEMBER 2023

www.ti.com

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