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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TPS70445PWPR датащи(PDF) 29 Page - Texas Instruments |
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TPS70445PWPR датащи(HTML) 29 Page - Texas Instruments |
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29 / 44 page  TPS704xxPWP (FixedOutputOption) 0.22 F m 22 F m 0.22 F m 250kW 250kW 47 F m >2V <0.7V >2V <0.7V EN1 EN2 EN1 EN2 V IN1 V IN2 V IN RESET V OUT1 V SENSE1 PG1 MR V SENSE2 V OUT2 PG2 V OUT2 RESET PG2 V OUT1 95% 95% EN2 EN1 V OUT1 V OUT2 PG2 PG1 MR MR (PG1tiedto ) RESET FAULTONV OUT1 NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh. B.Thetimingdiagramisnotdrawntoscale. 1 IN UVLO MR 120ms t 1 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 Application condition: VIN1 and VIN2 are tied to same fixed input voltage greater than VUVLO. PG1 is tied to MR. EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 (tied to MR) and PG2 are at logic low. Since MR is at logic low, RESET is also at logic low. When EN2 is taken to logic low, VOUT2 turns on. Later, when EN1 is taken to logic low, VOUT1 turns on. When VOUT2 reaches 95% of its regulated output voltage, PG2 goes to logic high. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When VIN1 is greater than VUVLO and MR (tied to PG2) is at logic high, RESET is pulled to logic high after a 120-ms delay. When a fault on VOUT1 causes it to fall below 95% of its regulated output voltage, PG1 (tied to MR) goes to logic low. Since MR is logic low, RESET goes to logic low. VOUT2 is unaffected. Figure 40. Timing When There is a Fault on VOUT1 Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 29 |
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