TPS70302PWPR datasheet(29/48 Pages) TI2

29 / 48 page

VOUT2

VIN1

VIN2

SEQ

VOUT1

VSENSE1

PG1

MR2

RESET

MR1

VSENSE2

VOUT2

VOUT1

MR1

0.22 F

RESET

22 F

47 F

0.22 F

MR2

0.7V

TPS703xxPWP

(FixedOutputOption)

>2V

<0.7V

250kW

83%

95%

120ms

VOUT2

VOUT1

PG1

MR1

MR2

(MR2 tiedtoPG1)

RESET

SEQ

120ms

83%

95%

(see NoteA)

NOTEA:t :TimeatwhichbothV

andV

aregreaterthanthePGthresholdsand

islogichigh.

OUT1

OUT2

MR1

TPS70345, TPS70348

TPS70351, TPS70358

TPS70302

www.ti.com

SLVS285H – AUGUST 2000 – REVISED APRIL 2010

Application

conditions

not

shown

block

diagram:

VIN1 and VIN2 are tied to the same fixed input

voltage greater than VUVLO; SEQ is tied to logic

high; PG1 is tied to MR2; MR1 is initially at logic

high but is eventually toggled.

Explanation of timing diagrams:

EN is initially high; therefore, both regulators are

off and PG1 and RESET are at logic low. With

SEQ at logic high, when EN is taken low, VOUT2

turns on. VOUT1 turns on after VOUT2 reaches 83%

of its regulated output voltage. When VOUT1

reaches 95% of its regulated output voltage, PG1

(tied to MR2) goes to logic high. When both

VOUT1 and VOUT2 reach 95% of their respective

regulated output voltages and both MR1 and

MR2 (tied to PG1) are at logic high, RESET is

pulled to logic high after a 120 ms delay. When

MR1 is taken low, RESET returns to logic low but

the outputs remain in regulation. When MR1

returns to logic high, because both VOUT1 and

VOUT2 remain above 95% of their respective

regulated output voltages and MR2 (tied to PG1)

remains at logic high, RESET is pulled to logic

high after a 120 ms delay.

Figure 40. Timing When MR1 is Toggled

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