7.3 Feature Description

7.3.1 PWM Operation

The main control loop of the TPS54526 is an adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with

an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low ESR and ceramic output capacitors. It is stable with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. The MOSFET is turned off after the internal

one-shot timer expires. The one-shot timer is set by the converter input voltage, VIN, and the output voltage, VO,

to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control.

The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below

the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the

need for ESR induced output ripple from D-CAP2™ mode control.

7.3.2 PWM Frequency and Adaptive On-Time Control

TPS54526 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The

TPS54526 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to

set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the

output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

7.3.3 Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN pin becomes high, 6 μA current begins charging the capacitor

which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.

The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is

6 μA.

(nF) x V

(nF) x 0.765 1.1

REF

SS

SS

t

(ms) =

=

SS

I

( A)

SS

C

1.1

C

6

´

m

´

(1)

The TPS54526 contains a unique circuit to prevent current from being pulled from the output during startup if

the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft

start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by

starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a

cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.

This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and

ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to

normal mode operation.

7.3.4 Power Good

The TPS54526 has power-good open drain output. The power good function is activated after soft start has

finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage

is within -10% of the target value, internal comparators detect power good state and the power good signal

becomes high. Rpg resister value ,which is connected between PG and VREG5, is required from 25kΩ to

150kΩ. If the feedback voltage goes under 15% of the target value, the power good signal becomes low after a 5

μs internal delay.

7.3.5 VREG5

VREG5 is an internally generated voltage source used by the TPS54526. It is derived directly from the input

voltage and is nominally regulated to 5.5 V when the input voltage is above 5.6 V. The output of the VREG5

regulator is the input to the internal UVLO function. VREG5 must be above the UVLO wake up threshold voltage

(3.6 V typical) for the TPS54526 to function. Connect a 1 µF capacitor between pin 3 of the TPS54526 and

power ground for proper regulation of the VREG5 output. The VREG5 output voltage is available for external

use. It is recommended to use no more than 5 mA for external loads. The VREG5 output is disabled when the

TPS54526 EN pin is open or pulled low.

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TPS54526

SLVSB84D – MAY 2012 – REVISED APRIL 2021

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