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TPS84A20

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SLVSBC6C – MARCH 2013 – REVISED DECEMBER 2019

Product Folder Links: TPS84A20

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Copyright © 2013–2019, Texas Instruments Incorporated

Table 2. Pin Descriptions

TERMINAL

DESCRIPTION

NAME

NO.

AGND

2

Zero volt reference for the analog control circuit. These pins are not connected together internal to the

device and must be connected to one another using an AGND plane of the PCB. These pins are associated

with the internal analog ground (AGND) of the device. See Layout Considerations.

23

PGND

20

This is the return current path for the power stage of the device. Connect these pins to the load and to the

bypass capacitors associated with PVIN and VOUT.

21

31

32

33

VIN

3

Input bias voltage pin. Supplies the control circuitry of the power converter. Connect this pin to the input bias

supply. Connect bypass capacitors between this pin and PGND.

PVIN

1

Input switching voltage. Supplies voltage to the power switches of the converter. Connect these pins to the

input supply. Connect bypass capacitors between these pins and PGND.

11

12

39

40

VOUT

34

Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output

load and connect external bypass capacitors between these pins and PGND.

35

36

37

38

41

PH

10

Phase switch node. These pins must be connected to one another using a small copper island under the

device for thermal relief. Do not place any external component on these pins or tie them to a pin of another

function.

13

14

15

16

17

18

19

42

DNC

5

Do not connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These

pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.

9

24

ISHARE

25

Current share pin. Connect this pin to other TPS84A20 devices ISHARE pin when paralleling multiple

TPS84A20 devices. When unused, treat this pin as a Do Not Connect (DNC) and leave it isolated from all

other signals or ground.

OCP_SEL

4

Over current protection select pin. Leave this pin open for hiccup mode operation. Connect this pin to AGND

for cycle-by-cycle operation. See Overcurrent Protection for more details.

ILIM

6

Current limit pin. Leave this pin open for full current limit threshold. Connect this pin to AGND to reduce the

current limit threshold by approximately 20%.

SYNC_OUT

7

Synchronization output pin. Provides a 180° out-of-phase clock signal.

PWRGD

8

Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately

±6% out of regulation. A pullup resistor is required.

RT/CLK

22

This pin is connected to an internal frequency setting resistor which sets the default switching frequency. An

external resistor can be connected from this pin to AGND to increase the frequency. This pin can also be

used to synchronize to an external clock.

VADJ

26

Connecting a resistor between this pin and AGND sets the output voltage.

SENSE+

27

Remote sense connection. This pin must be connected to VOUT at the load or at the device pins. Connect

this pin to VOUT at the load for improved regulation.