ADPL12005/ADPL12006

20V, 5A/6A Fully Integrated Synchronous Buck

Converters

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Table 2. Configurations for Low-IQ Operation

CONTROLLER

TARGET

MODE

EN = High, SYNC = BIAS

EN = High

FPWM (high IQ)

EN = High, SYNC = Low

EN = High

Skip mode (low IQ)

EN = High, SYNC = Low

EN = Low

Standby mode (ultra-low IQ)

EN = Low

EN = High

Not allowed

Setting Output Voltage

For setting the output voltage to a value, connect a resistor-divider between OUT, FB, and GND as shown in Figure 1.

An identical but separate resistor-divider for controller and target is recommended.

PCB Layout Guidelines

Careful Printed circuit board (PCB) layout is critical to achieve low switching losses and clean, stable operation. Use a

multilayer board whenever possible for better noise immunity and power dissipation. See Figure 3 and the following

guidelines for a good PCB layout:

1) Use the correct footprint for the IC and place as many copper planes as possible under the IC footprint to ensure

efficient heat transfer.

2) Place the ceramic input-bypass capacitors, CBP and CIN, as close as possible to the SUP and PGND pins on both

sides of the IC. Use low-impedance connections (no vias or other discontinuities) between the capacitors and IC pins.

CBP should be located closest to the IC and should have very good high-frequency performance (small package size

and high capacitance). This will provide the best EMI rejection and minimize internal noise on the device, which can

degrade performance.

3) Place the inductor (L), output capacitors (COUT), bootstrap capacitor (CBST), and BIAS capacitor (CBIAS) in such a

way as to minimize the area enclosed by the current loops. Place the inductor (L) as close as possible to the IC LX

pin and minimize the area of the LX node. Place the output capacitors (COUT) near the inductor so that the ground

side of COUT is near the CIN ground connection to minimize the current-loop area. Place the BIAS capacitor (CBIAS)

next to the BIAS pin.

4) Place the bootstrap capacitor CBST close to the IC and use short, wide traces to minimize the loop area to minimize

the parasitic inductance. Use the nearest layer for return trace (CBST to LX) to minimize the inductance further. High

parasitic inductance can impact switching speed (increase switching losses) and cause high dv/dt noise.

5) Use a continuous copper GND plane on the layer next to the IC to shield the entire circuit. GND should also be poured

around the entire circuit on the top side. Ensure that all heat-dissipating components have adequate connections to

copper for cooling. Use multiple vias to interconnect GND planes/areas for low impedance and maximum heat

dissipation. Place vias at the GND terminals of the IC and input/output/ bypass capacitors. Do not separate or isolate

PGND and GND connections with separate planes or areas.

6) Place the feedback resistor-divider (if used) near the IC and route the feedback and OUT connections away from the

inductor, LX node and other noisy signals.