9 Power Supply Recommendations

This family of devices are passive ESD protection devices and there is no need to power them. Care should be

taken to not violate the maximum voltage specification to ensure that the device functions properly. The D+ and

D– lines share a TVS diode which can tolerate up to 6 V.

10 Layout

10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible.

– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,

resulting in early system failures.

– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces

away from the protected traces which are between the TVS and the connector.

• Route the protected traces as straight as possible.

• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded

corners with the largest radii possible.

– Electric fields tend to build up on corners, increasing EMI coupling.

Refer to Figure 10-1, the TPD2EUSB30/A are offered in space saving DRT package. The DRT is a 1-mm ×

1-mm package with flow-through pin-mapping for the high-speed differential lines. The TPD4EUSB30 is offered

in space saving DQA package. The DQA is a 1-mm × 2.5-mm package with flow-through pin-mapping for the

high-speed differential lines. It is recommended to place the package right next to the USB 3.0 connector.

The GND pin should connected to GND plane of the board through a large VIA. If a dedicated GND plane is

not present right underneath, it is recommended to route to the GND plane through a wide trace. The current

associated with IEC ESD stress can be in the range of 30Amps or higher momentarily. A good, low impedance

GND path ensures the system robustness against IEC ESD stress.

The TPDxEUSB30/A can provide system level ESD protection to the high-speed differential ports (> 5 Gbps data

rate). The flow-through package offers flexibility for board routing with traces up to 15 mills wide. It allows the

differential signal pairs couple together right after they touch the ESD ports of the TPDxEUSB30/A.

www.ti.com

TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30

SLVSAC2G – AUGUST 2010 – REVISED JUNE 2021

Copyright © 2022 Texas Instruments Incorporated

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Product Folder Links: TPD2EUSB30 TPD2EUSB30A TPD4EUSB30