VDD

VDD

VSS

VSS

Output

300 Ÿ

35 pF

SELx

GND

VIN

3 V

VIN

0 V

50%

50%

tON

tOFF

0.1 VS

0.9 VS

Output

VS

Sx

Dx

VS

0 V

3 V

50%

50%

VIN

TMUX6112

TMUX6111

Figure 8-5. Turn-On and Turn-Off Time Measurement Setup

8.1.6 Charge Injection

The TMUX6111, TMUX6112, and TMUX6113 have a simple transmission-gate topology. Any mismatch in

capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source

during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the

device is known as charge injection, and is denoted by the symbol QINJ. Figure 8-6 shows the setup used to

measure charge injection.

VS

VOUT

VDD

VDD

VSS

VSS

Output

1 nF

SELx

GND

VIN

3 V

VIN

0 V

Output

RS

Sx

Dx

VS

0 V

3 V

VIN

TMUX6112

TMUX6111

QINJ = CL ×

VOUT

Figure 8-6. Charge-Injection Measurement Setup

8.1.7 Off Isolation

Off isolation is defined as the voltage at the drain pin (Dx) of the TMUX6111, TMUX6112, and TMUX6113 when

a 1-VRMS signal is applied to the source pin (Sx) of an OFF switch. Figure 8-7 shows the setup used to measure

off isolation. Use Equation 2 to compute off isolation.

TMUX6111, TMUX6112, TMUX6113

SCDS383F – AUGUST 2018 – REVISED JULY 2025

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