AD4084BBCZ datasheet(58/94 Pages) AD

58 / 94 page

Data Sheet

AD4084

DIGITAL FEATURES

analog.com

Rev. 0 | 58 of 94

Asynchronous Read Access

Access to the FIFO data is made through either a LVDS configu-

ration (single lane only) or the multi-output SPI configuration of

the data interface after the capture has completed. As a result,

access is asynchronous to the capture process, and there are no

specific timing restrictions between the conversion and interface

clocks. Synchronization between the data FIFO and the data

interface clock domain requires each read access to begin with

a header followed by a transfer of M bytes of conversion data;

where M equals the product of the total number of results specified

in the FIFO_WATERMARK register (Address 0x1D and Address

0x1E) and the integer length in bytes (for SPI data interface) of a

single conversion result. Note that the number of active data lanes

reduces the access period by a factor of 2 for each doubling of the

number of active lanes.

CNV+

CNV-

FIFO_FULL

FIFO_READ_DONE

DCS

...

Number of DCLK = [(16*N)+8]

DCLK

SDOA

8'hAA

D15

[N]

D14

[N]

D13

[N]

D12

[N]

D11

[N]

D10

[N]

[1]

D15

[0]

D14

[0]

D13

[0]

SDOB

SDOC

SDOD

N+1

N+2

N+3

N = WATERMARK

MSB

MSB-1

Last Burst Results Loaded

FIFO Write Access Disabled

Read Access Initiated

FIFO Synchronized.

FIFO Full Flag Cleared

Last sample transferred to interface.

FIFO Full Empty Asserted

Figure 88. Asynchronous Capture Read Timing, Data FIFO Enabled, Single Data Lane

CNV+

CNV-

FIFO_FULL

FIFO_READ_DONE

DCS

...

Number of DCLK = [(4*N)+8]

DCLK

8'hAA

D12

[N]

[1]

D12

[0]

SDOA

8'hAA

D13

[N]

[1]

D13

[0]

SDOB

8'hAA

D14

[N]

D10

[N]

[1]

D14

[0]

D10

[0]

SDOC

8'hAA

D15

[N]

D11

[N]

[1]

D15

[0]

D11

[0]

SDOD

N+1

N+2

N+3

N = WATERMARK

MSB-1

MSB

Last Burst Results Loaded

FIFO Write Access Disabled

Read Access Initiated

FIFO Synchronized.

FIFO Full Flag Cleared

Last sample transferred to interface.

FIFO Full Empty Asserted

Figure 89. Asynchronous Capture Read Timing, Data FIFO Enabled, Quad Data Lane Configuration

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