THS3095D datasheet(24/46 Pages) TI2

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9.4 Layout

9.4.1 Layout Guidelines

To optimize performance with a high-frequency amplifier, such as the THS309x, pay careful attention to board

layout parasitic and external component types.

Recommendations to optimize performance include the following:

• Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the

output and input pins can cause instability. To reduce unwanted capacitance, open a window around the

signal I/O pins in all of the ground and power planes around those pins. Otherwise, keep ground and power

planes unbroken elsewhere on the board.

• Minimize the distance [< 0.25 inch (6.35 mm)] from the power supply pins to the high-frequency 0.1

‑μF

and 100

‑pF decoupling capacitors. At the device pins, keep the ground and power plane layout away from

the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and

the decoupling capacitors. Always decouple the power-supply connections with these capacitors. Use larger

(6.8 μF or more) tantalum decoupling capacitors, effective at lower frequency, on the main supply pins. The

decoupling capacitors can be placed somewhat farther from the device, and can be shared among several

devices in the same area of the printed circuit board (PCB).

• Connections to other wideband devices on the board can be made with short direct traces or through

onboard transmission lines. For short connections, consider the trace and the input to the next device as a

lumped capacitive load. Use relatively wide traces [0.05 inch (1.3 mm) to 0.1 inch (2.54 mm)], preferably with

ground and power planes opened up around the traces. Estimate the total capacitive load and determine if

isolation resistors on the outputs are necessary. Low-parasitic capacitive loads (< 4 pF) may not need an

RISO because the THS309x are nominally compensated to operate with a 2-pF parasitic load. Higher parasitic

capacitive loads without an RISO are allowed as the signal gain increases (increasing the unloaded phase

margin).

9.4.1.1 PowerPAD Design Considerations

The THS309x are available in a thermally-enhanced PowerPAD family of packages. These packages are

constructed using a downset leadframe on which the die is mounted [see Figure 9-6(a) and Figure 9-6(b)]. This

arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see

Figure 9-6(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance

can be achieved by providing a good thermal path away from the thermal pad. Note that devices such as the

THS309x have no electrical connection between the PowerPAD and the die.

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.

During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be

soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,

heat can be conducted away from the package into either a ground plane or other heat-dissipating device.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of

surface mount with the awkward mechanical methods of heatsinking.

DIE

Side View (a)

DIE

End View (b)

Thermal

Pad

Bottom View (c)

Figure 9-6. Views of Thermal Enhanced Package

Although there are many ways to properly heatsink the PowerPAD package, the following section lists the

recommended steps.

THS3091, THS3095

SLOS423K – SEPTEMBER 2003 – REVISED APRIL 2023

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