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TDP142

SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019

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8.3 Feature Description

8.3.1 DisplayPort

The TDP142 supports up to 4 DisplayPort lanes at data rates up to 8.1Gbps (HBR3). The TDP142 monitors the

native AUX traffic as it traverses between DisplayPort source and DisplayPort sink. For the purposes of reducing

power, the TDP142 manages the number of active DisplayPort lanes based on the content of the AUX

transactions. The TDP142 snoops native AUX writes to DisplayPort sink’s DPCD registers 0x00101

(LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE). TDP142 disables/enables lanes based on value

written to LANE_COUNT_SET. The TDP142 disables all lanes when SET_POWER_STATE is in the D3.

Otherwise active lanes will be based on value of LANE_COUNT_SET.

DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE

register. Once AUX snoop is disabled, management of TDP142 DisplayPort lanes are controlled through various

configuration registers. When TDP142 is enabled for GPIO mode (I2C_EN = "0"), the SNOOPENZ pin can be

used to disable AUX snooping. When SNOOPENZ pin is high, the AUX snooping functionality is disabled and all

four DisplayPort lanes will be active.

8.3.2 4-level Inputs

The TDP142 has (I2C_EN, A0, and DPEQ[1:0]) 4-level inputs pins that are used to control the equalization gain

and place TDP142 into different modes of operation. These 4-level inputs utilize a resistor divider to help set the

4 valid levels and provide a wider range of control settings. There are internal pull-up and pull-down and combine

with the external resistor connection to achieve the desired voltage level.

Table 1. 4-Level Control Pin Settings

LEVEL

SETTINGS

0

Option 1: Tie 1 k

Ω 5% to GND.

Option 2: Tie directly to GND.

R

Tie 20 k

Ω 5% to GND.

F

Float (leave pin open)

1

Option 1: Tie 1 k

Ω 5% to VCC.

Option 2: Tie directly to VCC.

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NOTE

All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal

pull-up and pull-down resistors will be isolated in order to save power.

8.3.3 Receiver Linear Equalization

The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in

the system before the input of the TDP142. The receiver overcomes these losses by attenuating the low

frequency components of the signals with respect to the high frequency components. The proper gain setting

should be selected to match the channel insertion loss before the input of the TDP142 receivers. Two 4-level

inputs pins enable up to 16 possible equalization settings. The TDP142 also provides the flexibility of adjusting

settings through I2C registers.