8.5 Electrical Characteristics (continued)

VDD = 12 V, 4.7-µF capacitor from VDD to GND, TA = TJ = –40°C to 105°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Bias voltage

Includes CS comp offset

5

25

50

mV

Input bias current

–1

uA

Propagation delay from CS to OUTx

ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV

25

40

ns

Propagation delay from CS to CLF

ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV

25

50

CURRENT SENSE DISCHARGE TRANSISTOR

Discharge resistance

IN = low, resistance from CS to AGND

10

35

75

Ω

OUTPUT DRIVERS

Source current(1)

VDD = 12 V, IN = high, OUT = 5 V

4

A

Sink current(1)

VDD = 12 V, IN = low, OUT = 5 V

4

Source current(1)

VDD = 4.75 V, IN = high, OUT = 0

2

Sink current(1)

VDD = 4.75 V, IN = low, OUT = 4.75 V

3

Rise time, tR (1)

CLOAD = 2.2 nF, VDD = 12 V

10

20

ns

Fall time, tF (1)

CLOAD = 2.2 nF, VDD = 12 V

10

15

Output with VDD < UVLO

VDD = 1.0 V, ISINK = 10 mA

0.8

1.2

V

Propagation delay from IN to OUTx, tD1 CLOAD = 2.2 nF, VDD = 12 V, CLK rising

20

35

ns

(1)

Ensured by design. Not 100% tested in production.

VIT−

10%

90%

INPUT

OUTPUT

VIT+

tD1

tF

tF

tD2

Figure 8-1. Timing Diagram

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UCD7100

SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021

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