UCD3138 datasheet(64/99 Pages) TI2

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2 B – QB2

( EDGEGEN )

2 A – QT 2

( EDGEGEN )

0 B –

QSYN 2,4

1 B –

QSYN 1,3

Current

Peak Level

3 A – QB1

( DPWM 1 C)

3 B – QT1

( DPWM 2 C)

Period Start

Period End

Chopping point

Y 1

Figure 10-7. Final 6 Gate Signals

Note how the falling edge of DPWM2AF aligns with the X1 edge, and how the rising edge of DPWM2BF aligns

with the X3 edge. The falling edges on DPWM2AF and DPWM3AF are caused by the peak detection logic. This

is fed through the Cycle By Cycle logic. The Cycle By Cycle logic also has a special feature to control the rising

edges of DPWM2BF (X1 and X3) and DPWM3BF (Y1 and Y3). It uses the value of Event3 – Event2 to control

the time between the edges. The same feature is used with DPWM0 and DPWM1 to control the X2 and Y2

signals. Using the other 2 DPWMs permits these signals to have a different dead time.

The same setup can be used for voltage mode control. In this case, the Filter output sets the timing of the falling

edge on DPWMxAF.

All DPWMs are configured in Normal mode, with CBC enabled. If external slope compensation is used,

DPWM1A and DPWM1B are used to reset the external compensator at the beginning of each half cycle. If

no PCMC event occurs, the values of Events 2 and 3 determine the locations of the edges, just as in open loop

mode.

10.2.2.6 System Initialization for PCM

PCM (Peak Current Mode) is a specialized configuration for the UCD3138x which involves several peripherals.

This section describes how it works across the peripherals.

10.2.2.6.1 Use of Front Ends and Filters in PSFB

All three front ends are used in PSFB. The same signals are used in the same places for both PCMC and

voltage mode. The same hardware can be used for both control modes, with the mode determined by which

firmware is loaded into the device. FE0 and FE1 are used with their associated filters, but Filter 2 is not used at

all.

FE0 – Vout – voltage loop

FE1 – Iout – current loop

FE2 – Ipri – PCM

In PCMC mode, FE2 is used for PCMC, and the voltage loop is normally used to provide the start point for the

compensation ramp. If the CPCC firmware detects a need for constant current mode, it switches to the current

loop for the start point.

UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

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