8

ICS853052AG REV. B OCTOBER 24, 2007

ICS853052

DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER

PRELIMINARY

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

Ω

transmission lines. Matched impedance techniques should be

used to maximize operating frequency and minimize signal dis-

tortion. Figures 2A and 2B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts

may exist and it would be recommended that the board design-

ers simulate to guarantee compatibility across all printed circuit

and clock component process variations.

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

This section shows examples of 5V LVPECL output termination.

Figure 3A shows standard termination for 5V LVPECL. The

termination requires matched load of 50

Ω resistors pull down to

Zo = 50 Ohm

R2

50

Zo = 50 Ohm

5V

3V

PECL

+

-

R1

50

5V

PECL

R4

84

5V

Zo = 50 Ohm

R3

84

R2

125

5V

PECL

PECL

+

-

Zo = 50 Ohm

R1

125

V

CC

- 2V = 3V at the receiver. Figure 3B shows Thevenin

equivalence of Figure 3A. In actual application where the 3V DC

power supply is not available, this approached is normally used.