7

ICS853017AM REV. B OCTOBER 24, 2007

ICS853017

QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER

PRELIMINARY

For applications not requiring the use of a clock input, it can be

left floating. Though not required, but for additional protection, a

1k

Ω resistor can be tied from the Dx input to ground.

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ V

CC

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

CC

= 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

VCC

R2

1K

V_REF

C1

0.1u

R1

1K

Single Ended Clock Input

PCLK

nPCLK