0.00

0.25

0.50

0.75

1.00

1.25

±6

±5

±4

±3

±2

±1

0

1

2

3

4

5

6

Input Voltage (V)

C003

±4000

±3000

±2000

±1000

0

1000

2000

±6

±5

±4

±3

±2

±1

0

1

2

3

4

5

6

Input Voltage (V)

C002

-0.00056

-0.00054

-0.00052

-0.0005

-0.00048

-0.00046

-0.00044

-0.00042

-0.0004

±6

±5

±4

±3

±2

±1

0

1

2

3

4

5

6

Input Voltage (V)

C001

17

REF2912, REF2920, REF2925

REF2930, REF2933, REF2940

www.ti.com

SBVS033C – JUNE 2002 – REVISED JUNE 2016

Product Folder Links: REF2912 REF2920 REF2925 REF2930 REF2933 REF2940

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Copyright © 2002–2016, Texas Instruments Incorporated

Typical Application (continued)

9.2.1 Design Requirements

•

Supply Voltage: 3.3 V

•

Maximum Input Voltage: ±6 V

•

Specified Input Voltage: ±5 V

•

ADC Reference Voltage: 1.25 V

The goal for this design is to accurately condition a ±5-V bipolar input voltage into a voltage suitable for

conversion by a low-voltage ADC with a 1.25-V reference voltage, VREF, and an input voltage range of VREF / 2.

The circuit should function with reduced performance over a wider input range of at least ±6 V to allow for easier

protection of overvoltage conditions.

9.2.2 Detailed Design Procedure

Figure 30 depicts a simplified schematic for this design showing the MSP430 ADC inputs and full input-

conditioning circuitry. The ADC is configured for a bipolar measurement where final conversion result is the

differential voltage between the voltage at the positive and negative ADC inputs. The bipolar, GND referenced

input signal must be level-shifted and attenuated by the operational amplifier so that the output is biased to VREF /

2 and has a differential voltage that is within the ±VREF / 2 input range of the ADC.

9.2.3 Application Curves

Figure 31. OPA317 Output Voltage vs Input Voltage

Figure 32. OPA317 Output Voltage Error vs Input Voltage

Figure 33. Output Code Error vs Input Voltage