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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OPA810IDBVT датащи(PDF) 36 Page - Texas Instruments |
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OPA810IDBVT датащи(HTML) 36 Page - Texas Instruments |
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36 / 52 page  8.4.2 Layout Example Place bypass capacitors close to power pins Place output r esi stors close to output pin to minimize para sitic capa citance Gro und and power plan e re mo ved from in ner layers. Gro und fill on outer layers a lso removed Gro und and power plan e e xist on inne r la yer s. Place bypass capacitors close to power pins Remove G ND and Power plan e und er o utp ut and inverting pins to minimize stray PCB capacitance CBYP RF RG + ± VS- CBYP VS+ Representative schematic of a single channe l 1 8 2 7 3 6 4 5 RS CBYP CBYP RS Remove G ND and Power plan e und er o utp ut and inverting pins to minimize stray PCB capacitance Place inpu t resistor close to pin 2 to minimize p arasitic ca pacita nce Place feedback r esistor on the bottom of PCB be tween pin s 2 and 6 RG Figure 8-19. Layout Recommendation OPA810 SBOS799E – AUGUST 2019 – REVISED AUGUST 2024 www.ti.com 36 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: OPA810 |
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