HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR

S-1155 Series

Seiko Instruments Inc.

13

Operation

1. Basic operation

Figure 11

shows the block diagram of the S-1155 Series.

is not influenced by the input voltage and temperature change, to the output transistor.

VOUT

*1

VSS

VIN

Error amplifier

Current

supply

−

+

Reference voltage

circuit

*1.

Parasitic diode

Figure 11

2. Output transistor

In the S-1155 Series, a low on-resistance P-channel MOS FET is used as the output transistor.

+ 0.3 V to prevent the voltage regulator from being damaged due to inverse