LP5569RTWR datasheet(24/93 Pages) TI2

24 / 93 page

start

MSB Chip Addr LSB

ack

MSB Register Addr LSB

ack

MSB

Data LSB

ack

stop

ack from slave

SCL

SDA

start

id = 32h

ack

addr = 40h

ack

address 40h data

stop

ADR6

bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

C Slave Address (chip address)

LP5569

SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017

www.ti.com

Product Folder Links: LP5569

Submit Documentation Feedback

Table 2. LP5569 Slave-Address Combinations

SLAVE ID

VERSION

ADDR

32h and 40h

GND

33h and 40h

SCL

34h and 40h

SDA

35h and 40h

VIN

42h and 40h

GND

43h and 40h

SCL

44h and 40h

SDA

45h and 40h

VIN

Figure 22. LP5569 Chip Address

8.5.1.5 Control Register Write Cycle

1. The master device generates a start condition.

2. The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).

3. The slave device sends an acknowledge signal if the slave address is correct.

4. The master device sends the control register address (8 bits).

5. The slave device sends an acknowledge signal.

6. The master device sends the data byte to be written to the addressed register.

7. The slave device sends an acknowledge signal.

8. If the master device sends further data bytes, the control register address of the slave is incremented by 1

after the acknowledge signal. In order to reduce program load time, the LP5569 device supports address

auto incrementation. The register address is incremented after each 8 data bits. For example, the whole

program memory page can be written in one serial-bus write sequence.

9. The write cycle ends when the master device creates a stop condition.

Figure 23. Write Cycle (W = Write; SDA = 0)

8.5.1.6 Control Register Read Cycle

1. The master device generates a start condition.

2. The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).

3. The slave device sends an acknowledge signal if the slave address is correct.

4. The master device sends the control register address (8 bits).

5. The slave device sends an acknowledge signal.

LP5569RTWR датащи(PDF) 24 Page - Texas Instruments

LP5569RTWR датащи(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

датащи скачать

ссылки URL