TJA =

TJ - TA

PD

Nack stop

address h´00 data

ack

r

id = h´47

rs

ack

addr = h´00

ack

w

id = h´47

start

scl

sda

start

msb

ID

lsb

w ack msb ADDRESS lsb ack

rs

msb

ID

lsb

r ack

msb

lsb

NA stop

DATA

ack from slave

repeated start

ack from slave

ack from slave

data from slave Nack from master

LP3947

www.ti.com

SNVS298B – NOVEMBER 2004 – REVISED APRIL 2013

w = write (sda = “0”)

r = read (sda = “1”)

ack = acknowledge (sda pulled low by either master or slave)

Nack = No Acknowledge

rs = repeated start

Figure 9. LP3947 (Slave) Register Read

THERMAL PERFORMANCE OF WSON PACKAGE

The LP3947 is a monolithic device with an integrated pass transistor. To enhance the power dissipation

performance, the Leadless Lead frame Package, or WSON, is used. The WSON package is designed for

improved thermal performance because of the exposed die attach pad at the bottom center of the package. It

brings advantage to thermal performance by creating a very direct path for thermal dissipation. Compared to the

traditional leaded packages where the die attach pad is embedded inside the mold compound, the WSON

reduces a layer of thermal path.

The thermal advantage of the WSON package is fully realized only when the exposed die attach pad is soldered

down to a thermal land on the PCB board and thermal vias are planted underneath the thermal land. Based on a

WSON thermal measurement, junction to ambient thermal resistance (

θJA) can be improved by as much as two

times if a WSON is soldered on the board with thermal land and thermal vias than if not.

An example of how to calculate for WSON thermal performance is shown below:

(2)

By substituting 37°C/W for

θJA, 125°C for TJ and 70°C for TA, the maximum power dissipation allowed from the

chip is 1.48W. If VCHG-IN is at 5.0V and a 3.0V battery is being charged, then 740 mA of ICHG can safely charge

the battery. More power can be dissipated at ambient temperatures below 70°C. Less power can be dissipated at

ambient temperatures above 70°C. The maximum power dissipation for operation can be increased by 27 mW

for each degree below 70°C, and it must be de-rated by 27 mW for each degree above 70°C.

LAYOUT CONSIDERATION

The LP3947 has an exposed die attach pad located at the bottom center of the WSON package. It is imperative

to create a thermal land on the PCB board when designing a PCB layout for the WSON package. The thermal

land helps to conduct heat away from the die, and the land should be the same dimension as the exposed pad

on the bottom of the WSON (1:1 ratio). In addition, thermal vias should be added inside the thermal land to

conduct more heat away from the surface of the PCB to the ground plane. Typical pitch and outer diameter for

these thermal vias are 1.27 mm and 0.33 mm respectively. Typical copper via barrel plating is 1oz although

thicker copper may be used to improve thermal performance. The LP3947 bottom pad is connected to ground.

Therefore, the thermal land and vias on the PCB board need to be connected to ground.

For more information on board layout techniques, refer to Application Note 1187 (SNOA401) “Leadless

Leadframe Package (LLP).” The application note also discusses package handling, solder stencil, and assembly.

Copyright © 2004–2013, Texas Instruments Incorporated

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