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STA680D датащи(PDF) 37 Page - STMicroelectronics

номер детали STA680D
подробное описание детали  Automotive HD Radio™ baseband receiver
PDF  48 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STA680D датащи(HTML) 37 Page - STMicroelectronics

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DS5877 Rev 13
37/48
STA680
Digital I/O and memory interfaces
47
Figure 13. Timing diagrams and waveform for the SDRAM interface
Table 17 reports the timing values for the SDRAM interface
For power saving and reduced interference on the board, the SDRAM speed can be
programmed to work at half speed with respect to the internal data processing:
Full Rate SW application: the SDRAM interface works at the same frequency as the
internal data processing (HD 1.0 and HD 1.5 applications supported);
Half Rate SW application: the SDRAM interface works at half frequency with respect to
the internal data processing (only available for HD 1.0 application upon specific
request).
Table 17. SDRAM interface timing values
Symbol
Parameter
Condition
Software
application
Min.
Max.
Unit
Tck
SCL clock period
Core in normal
drive
Full rate
7.35
-
ns
Half rate
12.05
-
Tch
CLK high level width
-
-
2.5
-
ns
Tcl
CLK low level width
-
-
2.5
-
ns
Toh
Data out hold time
-
-
0.9
-
ns
Tos
Data out setup time
-
-
1.5
-
ns
Tis
Data In setup time
-
-
0.8
-
ns
Tih
Data In hold time
-
-
1.6
-
ns
Tt
Transition time
-
-
-
1.2
ns



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