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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC582B54E3 датащи(PDF) 39 Page - STMicroelectronics |
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SPC582B54E3 датащи(HTML) 39 Page - STMicroelectronics |
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39 / 111 page  DS11597 Rev 5 39/111 SPC582B60x, SPC582B54x, SPC582B50x Electrical characteristics 40 |ΔPLL0PHI1SPJ|4 CC D PLL0_PHI1 single period jitter fPLL0IN = 20 MHz (resonator) fPLL0PHI1 = 40 MHz, 6-sigma pk-pk — — 300(5) ps ΔPLL0LTJ4 CC D PLL0 output long term jitter5 fPLL0IN = 20 MHz (resonator), VCO frequency = 800 MHz 10 periods accumulated jitter (80 MHz equivalent frequency), 6-sigma pk-pk — — ±250 ps 16 periods accumulated jitter (50 MHz equivalent frequency), 6-sigma pk-pk — — ±300 ps long term jitter (< 1 MHz equivalent frequency), 6-sigma pk-pk) — — ±500 ps IPLL0 CC D PLL0 consumption FINE LOCK state — — 6 mA 1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using internal RCOSC or external oscillator is used in functional mode. 2. Refer to Section 4.3: Operating conditions for the maximum operating frequency. 3. If the PLL0_PHI1 is used as an input for PLL1, then the PLL0_PHI1 frequency shall obey the maximum input frequency limit set for PLL1 (87.5 MHz, according to Table 20). 4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to the output CLKOUT pin. 5. VDD_LV noise due to application in the range VDD_LV = 1.20 V±5%, with frequency below PLL bandwidth (40 kHz) will be filtered. Table 19. PLL0 electrical characteristics (continued) Symbol C Parameter Conditions Value Unit Min Typ Max |
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