SPC563M64L7 datasheet(35/128 Pages) STMICROELECTRONICS

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SPC563M64x, SPC563M60x

Overview

127



Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended,

16 standard or 32 partial (8 bits) IDs, with individual masking capability



Selectable backwards compatibility with previous FlexCAN versions



Programmable clock source to the CAN Protocol Interface, either system clock or

oscillator clock



Listen only mode capability



Programmable loop-back mode supporting self-test operation



3 programmable Mask Registers



Programmable transmit-first scheme: lowest ID, lowest buffer number or highest

priority



Time Stamp based on 16-bit free-running timer



Global network time, synchronized by a specific message



Maskable interrupts



Warning interrupts when the Rx and Tx Error Counters reach 96



Independent of the transmission medium (an external transceiver is assumed)



Multi master concept



High immunity to EMI



Short latency time due to an arbitration scheme for high-priority messages



Low power mode, with programmable wake-up on bus activity

2.3.18

System timers

The system timers provide two distinct types of system timer:



Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)



Operating system task monitors using the System Timer Module (STM)

2.3.18.1

Periodic Interrupt Timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts

and periodic triggers. The PIT has no external input or output pins and is intended to be

used to provide system ‘tick’ signals to the operating system, as well as periodic triggers for

eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is

clocked by the crystal clock. This one channel is also referred to as Real Time Interrupt

(RTI) and is used to wakeup the device from low power stop mode.

The following features are implemented in the PIT:



5 independent timer channels



Each channel includes 32-bit wide down counter with automatic reload



4 channels clocked from system clock



1 channel clocked from crystal clock (wake-up timer)



Wake-up timer remains active when System STOP mode is entered. Used to restart

system clock after predefined timeout period



Each channel can optionally generate an interrupt request or a trigger event (to trigger

eQADC queues) when the timer reaches zero

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