LM46002PWPRG4 datasheet(21/54 Pages) TI2

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RFBT

RFBB

CFF

VOUT

1.0E+04

1.0E+05

1.0E+06

5.0

5.5

6.0

6.5

7.0

VIN (V)

Load=0.1A

Load=0.5A

Load=1A

Load=1.5A

Load=2A

C005

LM46002

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SNVSA13C – APRIL 2014 – REVISED APRIL 2019

Product Folder Links: LM46002

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Feature Description (continued)

Figure 42. Switching Frequency Decreases in Dropout Operation

VOUT = 5 V FS = 1 MHz

7.3.9 Internal Compensation and CFF

The LM46002 is internally compensated with RC = 400 kΩ and CC = 50 pF as shown in Functional Block

Diagram. The internal compensation is designed such that the loop response is stable over the entire operating

frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can

be low with all ceramic capacitors. An external feed-forward cap CFF is recommended to be placed in parallel

with the top resistor divider RFBT for optimum transient performance.

Figure 43. Feed-Forward Capacitor for Loop Compensation

The feedforward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of

the control loop to boost phase margin. The zero frequency can be found by

fZ-CFF = 1 / (2π × RFBT × CFF).

(8)

An additional pole is also introduced with CFF at the frequency of

fP-CFF = 1 / (2π × CFF × ( RFBT // RFBB)).

(9)

The CFF should be selected such that the bandwidth of the control loop without the CFF is centered between fZ-CFF

and fP-CFF. The zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The

pole fP-CFF helps maintaining proper gain margin at frequency beyond the crossover.

Designs with different combinations of output capacitors need different CFF. Different types of capacitors have

different Equivalent Series Resistance (ESR). Ceramic capacitors have the smallest ESR and need the most

CFF. Electrolytic capacitors have much larger ESR, and the ESR zero frequency would be low enough to boost

the phase up around the crossover frequency. Designs using mostly electrolytic capacitors at the output may not

need any CFF (see Equation 10):

fZ-ESR = 1 / (2π × ESR × COUT)

(10)

The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If

the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple

too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, calculate CFF based on

output capacitors used in the system. At cold temperatures, the value of CFF might change based on the

tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To

avoid this, more capacitance can be added to the output or the value of CFF can be reduced. See the Detailed

Design Procedure for the calculation of CFF.

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