LM46000PWPR datasheet(21/56 Pages) TI2

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RFBT

RFBB

CFF

VOUT

10000

100000

1000000

5.0

5.2

5.4

5.6

5.8

6.0

6.2

6.4

6.6

6.8

7.0

VIN (V)

Load = 0.01 A

Load = 0.1 A

Load = 0.5 A

C001

LM46000

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SNVSA45B – JUNE 2014 – REVISED MARCH 2018

Product Folder Links: LM46000

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Feature Description (continued)

Given fixed TON-MIN and TOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty

cycle. In the LM46000, frequency foldback scheme is employed to extend the maximum duty cycle when TOFF-MIN

is reached. The switching frequency decreases once longer duty cycle is needed under low VIN conditions. The

switching frequency can be decreased to approximately 1/10 of the programmed frequency by RT or the

synchronization clock. Such wide range of frequency foldback allows the LM46000 output voltage to stay in

regulation with a much lower supply voltage VIN. This leads to a lower effective dropout voltage. See Typical

Characteristics for more details.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size and efficiency. The maximum operatable supply voltage can be found by

VIN-MAX = VOUT / (FS × TON-MIN )

(6)

At lower supply voltage, the switching frequency decreases once TOFF-MIN is tripped. The minimum VIN without

frequency foldback can be approximated by

VIN-MIN = VOUT / (1 – FS × TOFF-MIN )

(7)

Taking considerations of power losses in the system with heavy load operation, VIN-MIN is higher than the result

calculated in Equation 7 . With frequency foldback, VIN-MIN is lowered by decreased FS. Figure 42 gives an

example of how FS decreases with decreasing supply voltage VIN at drop-out operation.

Figure 42. Switching Frequency Decreases in Dropout Operation

VOUT = 5 V FS = 1 MHz

7.3.9 Internal Compensation and CFF

The LM46000 is internally compensated with RC = 400 kΩ and CC = 50 pF as shown in Functional Block

Diagram. The internal compensation is designed such that the loop response is stable over the entire operating

frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can

be low with all ceramic capacitors. An external feed-forward cap CFF is recommended to be placed in parallel

with the top resistor divider RFBT for optimum transient performance.

Figure 43. Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the cross over frequency of

the control loop to boost phase margin. The zero frequency can be found by

fZ-CFF = 1 / ( 2π × RFBT × CFF )

(8)

An additional pole is also introduced with CFF at the frequency of

fP-CFF = 1 / ( 2π × CFF × ( RFBT // RFBB ))

(9)

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