SPSB100 datasheet(212/213 Pages) STMICROELECTRONICS

212 / 213 page

Figure 53.

Current limitation curves of BUCK1, 2 for Vout 5 V ........................................... 85

Figure 54.

Current limitation curves of BUCK1, 2 for Vout 6.5 V ......................................... 86

Figure 55.

Vout = 3.3 V and VIN3 = 5 V .......................................................... 88

Figure 56.

Vout = 1.25 V and VIN3 = 3.3 V ........................................................ 88

Figure 57.

Vout = 1.2 V and VIN3 = 3.3 V ......................................................... 89

Figure 58.

Vout = 1.1 V and VIN3 = 3.3 V ......................................................... 89

Figure 59.

Vout = 0.98 V and VIN3 = 3.3 V ........................................................ 89

Figure 60.

Load transient BUCK3 at 0.98 V ....................................................... 90

Figure 61.

Load transient BUCK3 at 3.3 V ........................................................ 90

Figure 62.

Line transient BUCK3 at 0.98 V ....................................................... 90

Figure 63.

Line transient BUCK3 at 3.3 V ........................................................ 91

Figure 64.

Watchdog early, late and safe windows .................................................. 93

Figure 65.

Watchdog timing .................................................................. 94

Figure 66.

SPI - Transfer timing diagram ......................................................... 99

Figure 67.

SPI - Input timing ................................................................. 99

Figure 68.

SPI - Output timing ............................................................... 100

Figure 69.

SPI CSN - Output timing ........................................................... 101

Figure 70.

SPI - CSN low to high transition and global status bit access .................................. 101

Figure 71.

Typical application circuit ........................................................... 106

Figure 72.

Assembly top ................................................................... 194

Figure 73.

Inner 1 (ground) ................................................................. 195

Figure 74.

Inner 2 (ground and signal) ......................................................... 195

Figure 75.

Assembly bottom ................................................................ 196

Figure 76.

Solder mask defined (SMD) ......................................................... 197

Figure 77.

VFQFN56+4L (8x8x0.9 mm exp. pad down) package outline .................................. 198

SPSB100

List of figures

DS14640 - Rev 2

page 212/213

SPSB100 датащи(PDF) 212 Page - STMicroelectronics

SPSB100 датащи(HTML) 212 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL