SPSB100 datasheet(211/213 Pages) STMICROELECTRONICS

211 / 213 page

List of figures

Figure 1.

Block diagram .................................................................... 3

Figure 2.

Pin connection (top view) ............................................................. 4

Figure 3.

VFQFN56+4L printed circuit board 4 layers - Top layer ....................................... 10

Figure 4.

Max power dissipation vs ambient temperature for case "A" and case "B" .......................... 11

Figure 5.

Configuration 1: direct supply of the microcontroller core ...................................... 12

Figure 6.

Configuration 2: direct supply of the microcontroller core by internal SMPS ......................... 13

Figure 7.

Boost controller block diagram ........................................................ 14

Figure 8.

Boost controller disabled block diagram .................................................. 15

Figure 9.

Battery plug/unplug behavior ......................................................... 15

Figure 10.

Battery drop behavior .............................................................. 16

Figure 11.

Behavior on battery over voltage....................................................... 17

Figure 12.

State machine without fault transitions ................................................... 23

Figure 13.

State machine details with WD trig and FCCU monitor faults management .......................... 24

Figure 14.

State machine details on power-up fault (1) ............................................... 25

Figure 15.

State machine details on power-up fault (2) ............................................... 26

Figure 16.

State machine details onTSDC fault .................................................... 27

Figure 17.

Regulator faults reaction with REGFAIL_GO_REC = 1........................................ 28

Figure 18.

Regulator faults reaction with REGFAIL_GO_REC = 0........................................ 29

Figure 19.

FBB pin voltage fault reaction ......................................................... 30

Figure 20.

VS pin voltage fault reaction .......................................................... 30

Figure 21.

State machine ................................................................... 31

Figure 22.

Power-up sequence ............................................................... 35

Figure 23.

Power-down sequence ............................................................. 36

Figure 24.

Procedure to program the NVM ....................................................... 37

Figure 25.

NFSO1 implementation details ........................................................ 42

Figure 26.

NFSO1 output pin behavior at battery plug ................................................ 43

Figure 27.

NFSO1 output pin behavior after a failure is detected ........................................ 43

Figure 28.

Boost and bypass Vds monitoring (extracted by application scheme) .............................. 50

Figure 29.

Thermal cluster identification ......................................................... 51

Figure 30.

HW low level monitors .............................................................. 52

Figure 31.

Logic BIST ...................................................................... 54

Figure 32.

SPI pin description ................................................................ 57

Figure 33.

SPI signal description .............................................................. 58

Figure 34.

SDI frame ...................................................................... 58

Figure 35.

SDO frame...................................................................... 60

Figure 36.

CRC (cyclic redundancy check) calculation ............................................... 63

Figure 37.

Window watchdog operation.......................................................... 64

Figure 38.

PMIC + MCU in RUN mode .......................................................... 65

Figure 39.

PMIC + MCU in Smart-Power mode .................................................... 66

Figure 40.

PMIC + MCU in Stand-By mode ....................................................... 67

Figure 41.

Vout = 6.5 V and VIN12 = 10 V at 400 kHz ................................................. 80

Figure 42.

Vout = 5.0 V and VIN12 = 10 V at 400 kHz ................................................. 80

Figure 43.

Vout = 3.3 V and VIN12 = 10 V at 400 kHz ................................................. 81

Figure 44.

Vout = 6.5 V and VIN12 = 10 V at 2.4 MHz................................................. 81

Figure 45.

Vout = 5.0 V and VIN12 = 10 V at 2.4 MHz................................................. 82

Figure 46.

Vout = 3.3 V and VIN12 = 10 V at 2.4 MHz................................................. 82

Figure 47.

Load transient curve for BUCK1, 2 at 3.3 V, f = 400 kHz....................................... 83

Figure 48.

Load transient curve for BUCK1, 2 at 3.3 V, f = 2.4 MHz....................................... 83

Figure 49.

Load transient curve for BUCK1, 2 at 5 V, f = 2.4 MHz ........................................ 83

Figure 50.

Line transient curve for BUCK1, 2 at 3.3 V ................................................ 84

Figure 51.

Line transient curve for BUCK1, 2 at 5 V ................................................. 84

Figure 52.

Current limitation curves of BUCK1, 2 for Vout 3.3 V ......................................... 85

SPSB100

List of figures

DS14640 - Rev 2

page 211/213

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