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SPSB100 датащи(PDF) 190 Page - STMicroelectronics |
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SPSB100 датащи(HTML) 190 Page - STMicroelectronics |
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190 / 213 page ![]() Bit Name Description 20 BUCK2_FBLOSS 1: BUCK2 FB pin detection 0: No error 19 BUCK1_FBLOSS 1: BUCK1 FB pin detection 0: No error 18 NVM_COMPARE_ENA_STATUS 1: Status bit from ST_NVM to NVM_COMPARE_DISABLE inverted bit for user read 17 WD_TIME_STATUS_3 Live bit 16 WD_TIME_STATUS_2 Live bit Table 314. DSR18 (0x32) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) WD_TIME_STATUS_1 WD_TIME_STATUS_0 VBUCK3_ENA_STATUS VBUCK2_ENA_STATUS VBUCK1_ENA_STATUS LDO1_ENA_STATUS OUTHS_ENA_STATUS LOW_STATUS Watchdog time status bit 1 Watchdog time status bit 0 VBUCK3 enable status bit VBUCK2 enable status bit VBUCK1 enable status bit LDO1 enable status bit OUTHS enable status bit LOW status bit Table 315. DSR18 (0x32) description Bit Name Description 15 WD_TIME_STATUS_1 Live bit 14 WD_TIME_STATUS_0 Live bit 13 VBUCK3_ENA_STATUS Live bit 12 VBUCK2_ENA_STATUS Live bit 11 VBUCK1_ENA_STATUS Live bit 10 LDO1_ENA_STATUS Live bit 9 OUTHS_ENA_STATUS Live bit 8 LOW_STATUS Live bit 1: Watchdog is counting in LOW. Current window is LOW_SET 0: Watchdog is not counting in LOW. Current window is WD_TIME_STATUS Table 316. DSR18 (0x32) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R) 0 (R) 0 (R) 0 (R) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) BOOST_ENA_STATUS FCCU_ENA_STATUS RES RES CRC3 CRC2 CRC1 CRC0 Boost enable status bit FCCU enable status bit Reserved bit Reserved bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 317. DSR18 (0x32) LSB description Bit Name Description 7 BOOST_ENA_STATUS Live bit 6 FCCU_ENA_STATUS Live bit 5 RES Reserved 4 RES Reserved 3 CRC 3 SPSB100 SPI registers DS14640 - Rev 2 page 190/213 |
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