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SPSB100 датащи(PDF) 189 Page - STMicroelectronics |
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SPSB100 датащи(HTML) 189 Page - STMicroelectronics |
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189 / 213 page ![]() Table 309. DSR17 (0x31) description Bit Name Description 15 RES Reserved 14 RES Reserved 13 FBB_9 Voltage level on FBB pin Bits cannot be cleared (a clear command generates a SPI_UNDEF_ADD flag) 12 FBB_8 11 FBB_7 10 FBB_6 9 FBB_5 8 FBB_4 Table 310. DSR17 (0x31) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R) 0 (R) 0 (R) 0 (R) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) FBB_3 FBB_2 FBB_1 FBB_0 CRC3 CRC2 CRC1 CRC0 FBB voltage Level bit 3 FBB voltage Level bit 2 FBB voltage Level bit 1 FBB voltage Level bit 0 Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 311. DSR17 (0x31) LSB description Bit Name Description 7 FBB_3 6 FBB_2 5 FBB_1 4 FBB_0 3 CRC 3 2 CRC 2 1 CRC 1 0 CRC 0 Table 312. DSR18 (0x32) MSB Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 - (R0) - (R0) - (R0) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) RES RES RES BUCK2_FBLOSS BUCK1_FBLOSS NVM_COMPARE_ENA_STATUS WD_TIME_STATUS_3 WD_TIME_STATUS_2 Reserved Reserved Reserved BUCK2 feedback loss bit BUCK1 feedback loss bit NVM compare enable status bit Watchdog time status bit 3 Watchdog time status bit 2 Table 313. DSR18 (0x32) MSB description Bit Name Description 23 RES Reserved 22 RES Reserved 21 RES Reserved SPSB100 SPI registers DS14640 - Rev 2 page 189/213 |
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