SPSB100 datasheet(173/213 Pages) STMICROELECTRONICS

173 / 213 page

Bit

Name

Description

1: Input level is high

The bit shows the current state of SWDBG and cannot be cleared (“live bit”)

0: Input level is low

RES

Reserved

RES

Reserved

RES

Reserved

RES

Reserved

Table 242. DSR6 (0x26)

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

0 (RC1L)

0 (R)

0 (RC1L)

RES

FIN1_STATE IGN_STATE

WU_STATE

IGN_WAKE

WU_WAKE

RES

TIMER_WAKE

Reserved bit FIN1 state bit IGN state bit

Wake-up state

bit

IGN wake up bit Wake-up bit Reserved bit Timer wake up bit

Table 243. DSR6 (0x26) description

Bit

Name

Description

RES

Reserved

FIN1_STATE

state of FIN1 input

1: Input level is high

The bit shows the current state of FIN1 and cannot be cleared (“live bit”)

0: Input level is low

IGN_STATE

state of IGN input

1: Input level is high

The bit shows the momentary status of IGN and cannot be cleared (“live bit”)

Note that the status is only valid if IGN is configured as wake-up input in configuration register (0x05).

Otherwise this bit is read at its previous logic state

0: Input level is low

WU_STATE

state of WU input

1: Input level is high

The bit shows the momentary status of WU and cannot be cleared (“live bit”)

Note that the status is only valid if WU is configured as wake-up input in configuration register (0x05).

Otherwise this bit is read at its previous logic state

0: Input level is low

IGN_WAKE

Wake-up by IGN: shows wake up source

1: Wake-up

Bits are latched until a “read and clear” command

WU_WAKE

Wake-up by WU: shows wake up source

1: Wake-up

Bits are latched until a “read and clear” command

RES

Reserved

TIMER_WAKE

Wake-up by timer: shows wake up source

1: Wake-up

Bits are latched until a “read and clear” command

SPSB100

SPI registers

DS14640 - Rev 2

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