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SPSB100 датащи(PDF) 170 Page - STMicroelectronics |
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SPSB100 датащи(HTML) 170 Page - STMicroelectronics |
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170 / 213 page ![]() Table 233. DSR5 (0x25) MSB Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 - (R0) 0 (RC1L) 0 (R) 0 (R) 0 (R) 0 (RC1L) 0 (RC1L) 0 (RC1L) RES FP_READY BOOST_LEVEL_SET BOOST_ENA_STATUS BYPASS_STATUS BUCK3_PG_OK BUCK2_PG_OK BUCK1_PG_OK Reserved Full power Ready bit BOOST Level set bit BOOST enable status bit Bypass status bit BUCK3 power-good ok bit BUCK2 power-good ok bit BUCK1 power-good ok bit Table 234. DSR5 (0x25) MSB description Bit Name Description 23 RES Reserved 22 FP_READY 1: Transition from Low power to full power occurred. IRQ generated when this occurs 21 BOOST_LEVEL_SET 1: 9.5 V 0: 8.0 V 20 BOOST_ENA_STATUS 1: Boost switching ON 0: Boost switching OFF Live bit 19 BYPASS_STATUS 1: Bypass ON 0: Bypass OFF Live bit 18 BUCK3_PG_OK 1: Power-good reached after the regulator has been turned ON by power-up sequence or through SPI 0: PG not reached 17 BUCK2_PG_OK 1: Power-good reached after the regulator has been turned ON by power-up sequence or through SPI 0: PG not reached 16 BUCK1_PG_OK 1: Power-good reached after the regulator has been turned ON by power-up sequence or through SPI 0: PG not reached Table 235. DSR5 (0x25) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (RC1L) 0 (RC1L) DEV_STATE_5 DEV_STATE_4 DEV_STATE_3 DEV_STATE_2 DEV_STATE_1 DEV_STATE_0 DEEP-SLEEP_FROM_DO_POWER_DOWN_1 DEEP-SLEEP_FROM_DO_POWER_DOWN_0 Device state bit 5 Device state bit 4 Device state bit 3 Device state bit 2 Device state bit 1 Device state bit 0 DEEP-SLEEP from power down bit 1 DEEP-SLEEP from power down bit 0 Table 236. DSR5 (0x25) description Bit Name Description 15 DEV_STATE_5 14 DEV_STATE_4 13 DEV_STATE_3 12 DEV_STATE_2 11 DEV_STATE_1 10 DEV_STATE_0 Current state of state machine 00000: INIT … SPSB100 SPI registers DS14640 - Rev 2 page 170/213 |
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