L99VR02JTR datasheet(37/38 Pages) STMICROELECTRONICS

37 / 38 page

List of figures

Figure 1.

Functional block diagram of L99VR02J ................................................... 3

Figure 2.

Pins configuration .................................................................. 4

Figure 3.

Output voltage vs Tj ............................................................... 12

Figure 4.

Output voltage vs VS ............................................................... 12

Figure 5.

Drop voltage vs output current ........................................................ 12

Figure 6.

Current consumption vs output current .................................................. 12

Figure 7.

Current consumption vs input voltage (Io < 1 mA) ........................................... 12

Figure 8.

Current consumption vs input voltage (Io = 50 mA) .......................................... 12

Figure 9.

Current consumption vs input voltage (Io = 250 mA) ......................................... 13

Figure 10.

Short-circuit current vs Tj (Ishort pin tied to GND) ............................................ 13

Figure 11.

Short-circuit current vs Tj (Ishort pin floating) ............................................... 13

Figure 12.

Short-circuit current vs input voltage .................................................... 13

Figure 13.

Output voltage vs enable voltage (VO = 0.8 V) ............................................. 13

Figure 14.

Output voltage vs enable voltage (VO = 1.2 V) ............................................. 13

Figure 15.

Output voltage vs enable voltage (VO = 1.5 V) ............................................. 14

Figure 16.

Output voltage vs enable voltage (VO = 1.8 V) ............................................. 14

Figure 17.

Output voltage vs enable voltage (VO = 2.5 V) ............................................. 14

Figure 18.

Output voltage vs enable voltage (VO = 2.8 V) ............................................. 14

Figure 19.

Output voltage vs enable voltage (VO = 3.3 V) ............................................. 14

Figure 20.

Output voltage vs enable voltage (VO = 5 V) .............................................. 14

Figure 21.

VEN_high vs Tj .................................................................... 15

Figure 22.

VEN_low vs Tj .................................................................... 15

Figure 23.

Vwhth vs Tj ...................................................................... 15

Figure 24.

Vwlth vs Tj ...................................................................... 15

Figure 25.

ICWc vs Tj....................................................................... 15

Figure 26.

ICWd vs Tj....................................................................... 15

Figure 27.

PSRR ......................................................................... 16

Figure 28.

Load regulation test circuit ........................................................... 17

Figure 29.

Maximum load variation response (Vo = 5 V) .............................................. 17

Figure 30.

Maximum load variation response (Vo = 3.3 V) ............................................. 17

Figure 31.

Application schematic .............................................................. 18

Figure 32.

Application schematic – Post regulation .................................................. 18

Figure 33.

Behavior of output current versus regulated voltage VO ....................................... 19

Figure 34.

Ishort versus Rsh .................................................................. 19

Figure 35.

Example of output voltage selection .................................................... 20

Figure 36.

Typical example of enable control ...................................................... 21

Figure 37.

Reset timing diagram............................................................... 21

Figure 38.

Watchdog timing diagram............................................................ 22

Figure 39.

Thermal warning diagram............................................................ 23

Figure 40.

Square wave on TW pin generated during an overvoltage ..................................... 24

Figure 41.

Warning signal caused by overvoltage and thermal warning on TW pin ............................ 24

Figure 42.

Undervoltage lock out on output voltage.................................................. 25

Figure 43.

Typical application................................................................. 27

Figure 44.

PowerSSO-12 PC board ............................................................ 28

Figure 45.

Rthj-amb versus PCB copper area in open box free air condition.................................. 29

Figure 46.

PowerSSO-12 thermal impedance junction ambient single pulse................................. 29

Figure 47.

Thermal fitting model of a Vreg in PowerSSO-12 ............................................ 30

Figure 48.

PowerSSO-12 package dimensions .................................................... 31

Figure 49.

PowerSSO-12 tape and reel shipment (suffix “TR”) .......................................... 33

L99VR02J

List of figures

DS14076 - Rev 1

page 37/38

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