Functional description

L9352B

16/27

EN&IN = low means that at least one between enable and input is low. For the inputs IN=low

means also no input PWM. For the regulator input period longer than TDreg and for the

standard channel input period longer than TD.

A detected error is stored in an error register. The reset of this register is made with a timer

TD. With this approach all errors are present at the status output at least for the time TD.

All protection functions like short circuit of the output, over temperature, clock failure or

power-GND-loss in ON condition are stored into an internal “fail” register. The output is then

shut off. The register must be reset with a low signal at the input. A “low signal” means that

the input is low for a time longer than TD or TDReg for the related channel, otherwise it is

interpreted as a PWM input signal and the register is left in set mode.

Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail

register. This type of error is only delayed with the standard timer t

lf function.

Open load is detected for all four channels in on- and off-state.

Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33

* VS the error register is set and delayed with TD. A sink current stage pull the output down

to ground, with EN high. With EN low the output is floating in case of openload and the

detection is not assured. In the ON state the load current is monitored by the non-regulated

channels. If it drops below the specified threshold value IQU an open load is detected and

the error register is set and delayed with TD. A regulated channel detects the open load in

the on state with the current regulator error detection. If the output PWM reaches 90% for a

time longer than tRE than an error occurs. This could happen when no load is connected, the

resistivity of the load is too high or the supply voltage too low.

A clock failure (clock loss) is detected when the frequency becomes lower than f

CLK,min. All

status outputs are set on error and all power outputs are shut off. The status signals remain

in their state until the clock signal is present again. A clock failure during power on of VCC is

detected only on the regulated channels. The status outputs of the channel 1 and 2 are low

in this case.

Supply-VS-loss

X

X

tlf

timer TD

Clock control

X

X

no

in on: EN & IN = “LOW”

for TD or TDreg

in off: timer TD

Output voltage clamp active

X

(regulated

channels)

no

in on: EN & IN = “LOW”

for TD or TDreg

in off: timer TD

Table 7.

Error detection (continued)

ON State

EN &IN = HIGH

OFF State

EN &IN = LOW

Filter time

Reset done by