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L9305EP датащи(PDF) 44 Page - STMicroelectronics |
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L9305EP датащи(HTML) 44 Page - STMicroelectronics |
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44 / 107 page ![]() 8.4.2 Solenoid current control ADC check Each solenoid current control channel uses two independent current sense circuits, one for each HS and LS power stage. The current sense outputs are multiplexed into the ADC for digital processing and load current control. Each channel has a dedicated current measurement ADC and a redundant verification ADC. The verification is continuous during run time operation and requires no activation by the user. The comparison is done independently for each channel. Should the comparison check result in a difference of more than ADC_CHECK, the Solenoid ADC Mismatch Monitor bit, D[4] in the EXCEPTIONS1 register is set high. The fault is cleared upon reading. A simplified block diagram is shown in the figure below. Figure 20. ADC check block diagram + - + - + - Current digital conversion Valve currents Valve currents Current comparison Current digital conversion 1 ADCx ADCx 2 N 1 2 N GADG2709181327PS 8.4.3 Digital control loop logic BIST Digital control loop logic test verifies the logic controlling solenoid A/D data calibration and the current control loop. The test is performed independently on each channel. This self-test can be activated only if the channel is in tri-state mode as the control loop is disabled during this test. The sequence for initiating the self-test and reading the response is shown below: • In CONFIGURATION1 register, set Solenoid Logic Bist, bit D[10] =1 • Test status and results are available in the EXCEPTIONS1 register, bits D[8:7] Test results are cleared on register read. If test is running and channel is activated, result is unpredictable since CONFIGURATION1 register becomes write protected and test cannot be put back in IDLE. In this case it is better to de-activate the test before activating the channel. 8.4.4 Calibration data check Calibration and trimming data are used to compensate solenoid current control and internal reference circuitry. Data is stored in internal 8K bit NVM made of 256-bit sectors with the following architecture: Table 32. NVM memory map 256-bit calibration data field 120 bits data 8 bits CRC 120 bits data 8 bits CRC Upon Power on Reset (POR), the L9305 downloads calibration data from non-volatile memory into the appropriate local registers. During this process, the data is verified using the 8-bit CRC field. If a CRC failure is detected in data corresponding to analog trim data, the CRC error on CSA Compensation data bit, D[14] is set in the EXCEPTIONS 1 fault register. If a failure is detected in data corresponding to ADC compensation, the CRC error on A2D trimming data bit, D[13] is set in the EXCEPTIONS 1 fault register. In all cases, the register(s) affected by the faulty data are loaded to “0” to avoid unpredictable operation. Registers loaded with “0” due to a CRC fault will operate uncalibrated thus having reduced performance. 8.4.5 Diagnostic comparators All solenoid diagnostic comparators (overcurrent, off-state diagnostic, ground loss) have analog self-tests implemented to detect latent faults. The self-test must be enabled by the user with the channel in tri-state. The self-test is independent for each channel. Should the test fail, a diagnostic fault flag is set and is cleared upon reading the register. Should actuation be requested while the self-test is in process, the self-test will be terminated with an error (EXCEPTIONS1 register, self-test fail bit D[8:7] that indicates the case when both the comparators (LV and OV) fails and actuation will be permitted. L9305 Safety features DS12774 - Rev 10 page 44/107 |
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