Application information

L4938ED, L4938EPD

12/20

Doc ID 17243 Rev 2

In the standby mode when the output 2 is disabled, the current consumption of the device

(quiescent current) is less than 90 µA (14 V supply voltage).

To reduce the quiescent current peak in the undervoltage region and to improve the

transient response in this region, the dropout voltage is controlled. A second regulation path

keeps the output voltage without load below 5.5 V even at high temperatures.

3.3

Output 2 voltage

The output 2 regulator uses the same output structure as the standby regulator but rated for

the output current of 400 mA. The output voltage is internally fixed to 5 V if ADJ is

connected to VOUT2. The output 2 regulator can be switches OFF via the enable input.

Figure 4.

OUT2

Connecting a resistor divider R1E, R2E to the ADJ, OUT2 pin the output voltage 2 can be

programmed to the value of

with RADJ = 60 K to 150 K and VOUT1 = 4.95 to 5.05 V. For an exact calculation the

temperature coefficient (TC - 2000 pprm) of the internal resistor (RADJ) must be taken into

account. Pin ADJ in this mode should not have a capacitive burden because this would

reduce the phase margin of the regulator loop.

3.4

Reset circuit

The reset circuit supervises the standby output voltage. The reset output (RES) is defined

from VOUT ≥ 1 V. Even if VS is lacking, the reset generator is supplied by the output voltage

VOUT1.

The reset threshold of 4.7 V is defined with the internal reference voltage(a) and standby

output divider, when pin PR is left open. The reset threshold voltage can be programmed in

the range from 3.8 V to 4.7 V by connecting an external resistor from pin PR to GND.

V

OU T2

V

OUT1 1

R

1E R2E

R

ADJ

+

()

R

2E RAD J

⋅

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