Total power consumption can be calculated using the information provided in CMOS Power Consumption and

Cpd Calculation.

Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear

and Logic (SLL) Packages and Devices.

CAUTION

The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional

limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum

Ratings. These limits are provided to prevent damage to the device.

9.2.1.2 Input Considerations

Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do

not exceed the maximum input voltage range found in the Absolute Maximum Ratings.

Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is

completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used

sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used

for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the

CD74HC02, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor

value is often used due to these factors.

The CD74HC02 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the

Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power

consumption, and reduction in device reliability.

Refer to the Feature Description section for additional information regarding the inputs for this device.

9.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will

decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground

voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output

voltage as specified by the VOL specification in the Electrical Characteristics.

Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected

directly together. This can cause excessive current and damage to the device.

Two channels within the same device with the same input signals can be connected in parallel for additional

output drive strength.

Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.

Refer to Feature Description section for additional information regarding the outputs for this device.

9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout

section.

2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC02 to

the receiving device(s).

3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

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CD54HC02, CD74HC02

SCHS125D – MARCH 1998 – REVISED DECEMBER 2020

Copyright © 2020 Texas Instruments Incorporated

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Product Folder Links: CD54HC02 CD74HC02