STAMP0

List of figures

DocID028639 Rev 1

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List of figures

Figure 1: Pin connections (top view)...........................................................................................................8

Figure 2: Block diagram ............................................................................................................................10

Figure 3: PDM interface sampling control and usage example ................................................................14

Figure 4: Microphone sampling interface..................................................................................................15

Figure 5: Microphone processor internal blocks .......................................................................................15

Figure 6: Downsampling FIR frequency response (overall) .....................................................................16

Figure 7: STMRecomb block ....................................................................................................................17

Figure 8: Recombination bypass ..............................................................................................................18

Figure 9: High-level detection architecture ...............................................................................................20

Figure 10: RMS calculation data path.......................................................................................................21

Figure 11: IIR filter ....................................................................................................................................21

Figure 12: Serial output interface architecture..........................................................................................22

Figure 13: Channel mapping scheme.......................................................................................................23

Figure 14: Data and FSY change on the falling edges of SCK and are valid on the rising edges of SCK.

The frame starts on the rising edge of FSY (NO DELAY) ........................................................................24

Figure 15: Data and FSY change on the rising edges of SCK and are valid on the falling edges of SCK.

The frame starts on the rising edge of FSY (NO DELAY) ........................................................................24

Figure 16: Data and FSY change on the falling edges of SCK and are valid on the rising edges of

SCK.The frame starts on the falling edge of FSY (NO DELAY) ...............................................................24

Figure 17: Data and FSY change on the rising edges of SCK and are valid on the falling edges of

SCK.The frame starts on the falling edge of FSY (NO DELAY) ...............................................................25

Figure 18: Data and FSY change on the falling edges of SCK and are valid on the rising edges of

SCK.The frame starts on the rising edge of FSY (DELAYED) .................................................................25

Figure 19: Write mode sequence..............................................................................................................27

Figure 20: Read mode sequence .............................................................................................................27

Figure 21: Clock manager architecture.....................................................................................................28

Figure 22: PLL block internal architecture ................................................................................................29

Figure 23: VFQFPN (5 x 5 x 1.0 mm) 28L pitch 0.50 package outline .....................................................59

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