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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA381BWS датащи(PDF) 114 Page - STMicroelectronics |
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STA381BWS датащи(HTML) 114 Page - STMicroelectronics |
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114 / 174 page  Register description: Sound Terminal compatibility STA381BWS 114/174 DocID018937 Rev 7 happens. At the same time any processing related to the I2C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again. Note: Any mute or volume change causes some delay in the completion of the I2C operation due to the soft volume feature. The soft volume phase change must be finished before any clock desynchronization. 7.2.4 Delay serial clock enable 7.2.5 Channel input mapping Each channel received via I2S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel. Table 110. Delay serial clock enable Bit R/W RST Name Description 5 R/W 0 DSCKE 0: No serial clock delay 1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I2S master devices Table 111. Channel input mapping Bit R/W RST Name Description 6 R/W 0 C1IM 0: Processing channel 1 receives left I2S input 1: Processing channel 1 receives right I2S input 7 R/W 1 C2IM 0: Processing channel 2 receives left I2S input 1: Processing channel 2 receives right I2S input Obsolete Product(s) - Obsolete Product(s) |
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