STA381BWS datasheet(113/174 Pages) STMICROELECTRONICS

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STA381BWS

To make the STA381BWS work properly, the serial audio interface LRCKI clock must be

synchronous to the PLL output clock which means that:



the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on

the settings in Table 30 on page 61



the PLL must be locked.

If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the

STA381BWS will immediately mute the I2S PCM data out (provided to the processing block)

and it will freeze any active processing task.

To avoid any audio side effects (like pop noise), it is strongly recommended to soft-mute any

audio streams flowing into the STA381BWS data path before the desynchronization event

Table 109. Supported serial audio input formats for LSB-first (SAIFB = 1)

BICKI

SAI [3:0]

SAIFB

Interface format

32 * fs

1100

I2S 15-bit data

1110

Left/right-justified 16-bit data

48 * fs

0100

I2S 23-bit data

0100

I2S 20-bit data

1000

I2S 18-bit data

1100

LSB first I2S 16-bit data

0001

Left-justified 24-bit data

0101

Left-justified 20-bit data

1001

Left-justified 18-bit data

1101

Left-justified 16-bit data

0010

Right-justified 24-bit data

0110

Right-justified 20-bit data

1010

Right-justified 18-bit data

1110

Right-justified 16-bit data

64 * fs

0000

I2S 24-bit data

0100

I2S 20-bit data

1000

I2S 18-bit data

1100

LSB first I2S 16-bit data

0001

Left-justified 24-bit data

0101

Left-justified 20-bit data

1001

Left-justified 18-bit data

1101

Left-justified 16-bit data

0010

Right-justified 24-bit data

0110

Right-justified 20-bit data

1010

Right-justified 18-bit data

1110

Right-justified 16-bit data

Obsolete

Product(s)

- Obsolete

Product(s)

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