AMC7832IPAPRG4 datasheet(11/74 Pages) TI2

11 / 74 page

AMC7832

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SLAS836 – MARCH 2014

Electrical Characteristics (continued)

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of

the product containing it. AVDD = DVDD = +4.5 to +5.5-V, AVCC = +12-V, AVEE = -12-V, IOVDD = +1.8 to +5.5-V, AGND =

DGND = 0-V, AVSSA,B,C,D = 0-V (DAC groups in positive ranges) or -12-V (DAC groups in negative range), DAC output range

= 0 to 10-V for all groups, no load on the DACs, TA = -40°C to +105°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL REFERENCE SPECIFICATIONS

INTERNAL REFERENCE (Internal reference not accessable)

Initial accuracy

TA = 25°C

2.4925

2.5

2.5075

Reference temp. coefficient(8)

35 ppm/°C

REF_OUT[1-2] BUFFERS(9)

Reference buffer offset

TA = 25°C

±2.5

Capacitive load stability

100

INTERNAL ADC REFERENCE BUFFER

Reference buffer offset

TA = 25°C

±5

GENERAL SPECIFICATIONS

DIGITAL LOGIC: GPIO

VIH

High-level input voltage

IOVDD =+1.8 to +5.5-V

0.7×IOVDD

IOVDD = +1.8-V

0.45

VIL

Low-level input voltage

IOVDD = +2.7 to +5.5-V

0.3×IOVDD

IOVDD = +1.8-V, Iload = -2-mA

0.4

VOL

Low-level output voltage

IOVDD= +5.5-V, Iload = -5-mA

0.4

Input impedance

To IOVDD

Ω

DIGITAL LOGIC: All Except GPIO

VIH

High-level input voltage

IOVDD = +1.8 to +5.5-V

0.7×IOVDD

IOVDD = +1.8-V

0.45

VIL

Low-level input voltage

IOVDD = +2.7 to +5.5-V

0.3×IOVDD

VOH

High-level output voltage

Iload = -1-mA

IOVDD-0.4

VOL

Low-level output voltage

Iload = +1-mA

0.4

High-impedance leakage

±5

µA

High-impedance output capacitance

TIMING REQUIREMENTS

Reset delay

Delay to normal operation from reset

100

250

µs

Power-down recovery time

µs

Clamp shutdown delay

CL = 10nF

100

µs

Convert pulse width

Reset pulse width

POWER-SUPPLY REQUIREMENTS

IAVDD

AVDD supply current

IAVCC

AVCC supply current

IAVSS

AVSS supply current

–10

No DAC load, all DACs at 800h code and

ADC at the fastest auto conversion rate

IDVDD

DVDD supply current

IIOVDD

IOVDD supply current

µA

Power consumption

160

(8)

Not tested during production. Specified by design and characterization.

(9)

Intended to drive the VRANGEA,B,C,D inputs only. An external buffer amplifier with high impedance input is required to drive any

additional external load.

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